FD.io VPP  v16.06
Vector Packet Processing
asm_x86.h
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1 /*
2  * Copyright (c) 2015 Cisco and/or its affiliates.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at:
6  *
7  * http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 #ifndef included_asm_x86_h
16 #define included_asm_x86_h
17 
18 #include <vppinfra/format.h>
19 
20 typedef union {
21  struct {
24  };
25  u8 data[2];
27 
28 typedef struct {
29  /* Instruction name. */
30  char * name;
31 
32  /* X86 instructions may have up to 3 operands. */
33  x86_insn_operand_t operands[3];
34 
36 #define X86_INSN_FLAG_DEFAULT_64_BIT (1 << 0)
37 #define X86_INSN_FLAG_SET_SSE_GROUP(n) ((n) << 5)
38 #define X86_INSN_FLAG_GET_SSE_GROUP(f) (((f) >> 5) & 0x1f)
39 #define X86_INSN_FLAG_SET_MODRM_REG_GROUP(n) (((n) & 0x3f) << 10)
40 #define X86_INSN_FLAG_GET_MODRM_REG_GROUP(f) (((f) >> 10) & 0x3f)
41 } x86_insn_t;
42 
45 {
46  ASSERT (o < ARRAY_LEN (i->operands));
47  return i->operands[o].code != '_';
48 }
49 
50 #define foreach_x86_legacy_prefix \
51  _ (OPERAND_SIZE, 0x66) \
52  _ (ADDRESS_SIZE, 0x67) \
53  _ (SEGMENT_CS, 0x2e) \
54  _ (SEGMENT_DS, 0x3e) \
55  _ (SEGMENT_ES, 0x26) \
56  _ (SEGMENT_FS, 0x64) \
57  _ (SEGMENT_GS, 0x65) \
58  _ (SEGMENT_SS, 0x36) \
59  _ (LOCK, 0xf0) \
60  _ (REPZ, 0xf3) \
61  _ (REPNZ, 0xf2)
62 
63 #define foreach_x86_insn_parse_flag \
64  /* Parse in 32/64-bit mode. */ \
65  _ (PARSE_32_BIT, 0) \
66  _ (PARSE_64_BIT, 0) \
67  _ (IS_ADDRESS, 0) \
68  /* regs[1/2] is a valid base/index register */ \
69  _ (HAS_BASE, 0) \
70  _ (HAS_INDEX, 0) \
71  /* rex w bit */ \
72  _ (OPERAND_SIZE_64, 0)
73 
74 typedef enum {
75 #define _(f,o) X86_INSN_FLAG_BIT_##f,
78 #undef _
80 
81 typedef enum {
82 #define _(f,o) X86_INSN_##f = 1 << X86_INSN_FLAG_BIT_##f,
85 #undef _
87 
88 typedef struct {
89  /* Registers in instruction.
90  [0] is modrm reg field
91  [1] is base reg
92  [2] is index reg. */
93  u8 regs[3];
94 
95  /* Scale for index register. */
96  u8 log2_index_scale : 2;
97  u8 log2_effective_operand_bytes : 3;
98  u8 log2_effective_address_bytes : 3;
99 
101 
102  /* Parser flags: set of x86_insn_parse_flag_t enums. */
104 
106 
109 
110 u8 * x86_insn_parse (x86_insn_parse_t * p, u8 * code_start);
112 
113 #endif /* included_asm_x86_h */
sll srl srl sll sra u16x4 i
Definition: vector_sse2.h:267
u16 flags
Definition: asm_x86.h:35
x86_insn_operand_t operands[3]
Definition: asm_x86.h:33
#define foreach_x86_insn_parse_flag
Definition: asm_x86.h:63
char * name
Definition: asm_x86.h:30
#define always_inline
Definition: clib.h:84
int i32
Definition: types.h:81
always_inline uword x86_insn_operand_is_valid(x86_insn_t *i, uword o)
Definition: asm_x86.h:44
#define foreach_x86_legacy_prefix
Definition: asm_x86.h:50
long i64
Definition: types.h:82
format_function_t format_x86_insn_parse
Definition: asm_x86.h:111
x86_insn_parse_flag_bit_t
Definition: asm_x86.h:74
#define ARRAY_LEN(x)
Definition: clib.h:59
#define ASSERT(truth)
unsigned int u32
Definition: types.h:88
u8 *( format_function_t)(u8 *s, va_list *args)
Definition: format.h:48
u8 * x86_insn_parse(x86_insn_parse_t *p, u8 *code_start)
Definition: asm_x86.c:1494
u64 uword
Definition: types.h:112
unsigned short u16
Definition: types.h:57
unsigned char u8
Definition: types.h:56
x86_insn_t insn
Definition: asm_x86.h:107
x86_insn_parse_flag_t
Definition: asm_x86.h:81