16 #ifndef included_ixge_h 17 #define included_ixge_h 26 typedef volatile struct 29 u32 descriptor_address[2];
54 CLIB_PAD_FROM_TO (0x1c, 0x28);
81 u32 head_index_write_back_address[2];
100 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_LAYER2 (1 << (4 + 11)) 102 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4 (1 << (4 + 0)) 103 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4_EXT (1 << (4 + 1)) 104 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6 (1 << (4 + 2)) 105 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6_EXT (1 << (4 + 3)) 106 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_TCP (1 << (4 + 4)) 107 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_UDP (1 << (4 + 5)) 108 #define IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET(s) (((s) >> 21) & 0x3ff) 110 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE (1 << (0 + 0)) 111 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET (1 << (0 + 1)) 112 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_VLAN (1 << (0 + 3)) 113 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED (1 << (0 + 4)) 114 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED (1 << (0 + 5)) 115 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED (1 << (0 + 6)) 116 #define IXGE_RX_DESCRIPTOR_STATUS2_NOT_UNICAST (1 << (0 + 7)) 117 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_DOUBLE_VLAN (1 << (0 + 9)) 118 #define IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR (1 << (0 + 10)) 119 #define IXGE_RX_DESCRIPTOR_STATUS2_ETHERNET_ERROR (1 << (20 + 9)) 120 #define IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR (1 << (20 + 10)) 121 #define IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR (1 << (20 + 11)) 124 #define IXGE_RX_DESCRIPTOR_STATUS0_LAYER2_ETHERNET_TYPE(s) ((s) & 7) 132 #define IXGE_TX_DESCRIPTOR_STATUS0_ADVANCED (3 << 4) 133 #define IXGE_TX_DESCRIPTOR_STATUS0_IS_ADVANCED (1 << (8 + 5)) 134 #define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_REPORT_STATUS (8 + 3) 135 #define IXGE_TX_DESCRIPTOR_STATUS0_REPORT_STATUS (1 << IXGE_TX_DESCRIPTOR_STATUS0_LOG2_REPORT_STATUS) 136 #define IXGE_TX_DESCRIPTOR_STATUS0_INSERT_FCS (1 << (8 + 1)) 137 #define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET (8 + 0) 138 #define IXGE_TX_DESCRIPTOR_STATUS0_IS_END_OF_PACKET (1 << IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET) 139 #define IXGE_TX_DESCRIPTOR_STATUS1_DONE (1 << 0) 140 #define IXGE_TX_DESCRIPTOR_STATUS1_CONTEXT(i) ( (1 << 7) | ((i) << 4)) 141 #define IXGE_TX_DESCRIPTOR_STATUS1_IPSEC_OFFLOAD (1 << (8 + 2)) 142 #define IXGE_TX_DESCRIPTOR_STATUS1_INSERT_TCP_UDP_CHECKSUM (1 << (8 + 1)) 143 #define IXGE_TX_DESCRIPTOR_STATUS1_INSERT_IP4_CHECKSUM (1 << (8 + 0)) 144 #define IXGE_TX_DESCRIPTOR_STATUS0_N_BYTES_THIS_BUFFER(l) ((l) << 0) 145 #define IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET(l) ((l) << 14) 174 typedef volatile struct 187 CLIB_PAD_FROM_TO (0xc, 0x18);
193 CLIB_PAD_FROM_TO (0x1c, 0x20);
202 CLIB_PAD_FROM_TO (0x24, 0x28);
209 CLIB_PAD_FROM_TO (0x2c, 0x4c);
212 CLIB_PAD_FROM_TO (0x50, 0x200);
216 CLIB_PAD_FROM_TO (0x204, 0x600);
218 CLIB_PAD_FROM_TO (0x604, 0x700);
223 u32 mailbox_interrupt_status[4];
224 u32 mailbox_interrupt_enable[4];
225 CLIB_PAD_FROM_TO (0x730, 0x800);
231 CLIB_PAD_FROM_TO (0x804, 0x808);
233 CLIB_PAD_FROM_TO (0x80c, 0x810);
235 CLIB_PAD_FROM_TO (0x814, 0x820);
246 CLIB_PAD_FROM_TO (0x884, 0x888);
248 CLIB_PAD_FROM_TO (0x88c, 0x890);
256 CLIB_PAD_FROM_TO (0x89c, 0x900);
270 CLIB_PAD_FROM_TO (0xa04, 0xa90);
273 u32 status1_write_1_to_clear[4];
274 u32 enable1_write_1_to_set[4];
275 u32 enable1_write_1_to_clear[4];
276 CLIB_PAD_FROM_TO (0xac0, 0xad0);
277 u32 status1_enable_auto_clear[4];
278 CLIB_PAD_FROM_TO (0xae0, 0x1000);
283 CLIB_PAD_FROM_TO (0x2000, 0x2140);
284 u32 dcb_rx_packet_plane_t4_config[8];
285 u32 dcb_rx_packet_plane_t4_status[8];
286 CLIB_PAD_FROM_TO (0x2180, 0x2300);
289 u32 rx_queue_stats_mapping[32];
292 CLIB_PAD_FROM_TO (0x2384, 0x2410);
293 u32 fc_user_descriptor_ptr[2];
295 CLIB_PAD_FROM_TO (0x241c, 0x2420);
297 CLIB_PAD_FROM_TO (0x2424, 0x2430);
299 CLIB_PAD_FROM_TO (0x2434, 0x2f00);
303 CLIB_PAD_FROM_TO (0x2f08, 0x2f20);
305 CLIB_PAD_FROM_TO (0x2f24, 0x3000);
309 CLIB_PAD_FROM_TO (0x3004, 0x3008);
313 CLIB_PAD_FROM_TO (0x300c, 0x3020);
316 CLIB_PAD_FROM_TO (0x3024, 0x3028);
318 CLIB_PAD_FROM_TO (0x302c, 0x3190);
320 CLIB_PAD_FROM_TO (0x3194, 0x3200);
321 u32 flow_control_tx_timers[4];
322 CLIB_PAD_FROM_TO (0x3210, 0x3220);
323 u32 flow_control_rx_threshold_lo[8];
324 CLIB_PAD_FROM_TO (0x3240, 0x3260);
325 u32 flow_control_rx_threshold_hi[8];
326 CLIB_PAD_FROM_TO (0x3280, 0x32a0);
328 CLIB_PAD_FROM_TO (0x32a4, 0x3c00);
330 u32 rx_packet_buffer_size[8];
331 CLIB_PAD_FROM_TO (0x3c20, 0x3d00);
333 CLIB_PAD_FROM_TO (0x3d04, 0x4200);
338 CLIB_PAD_FROM_TO (0x4204, 0x4208);
346 CLIB_PAD_FROM_TO (0x4228, 0x4240);
367 CLIB_PAD_FROM_TO (0x424c, 0x425c);
370 CLIB_PAD_FROM_TO (0x4264, 0x4268);
374 CLIB_PAD_FROM_TO (0x426c, 0x4288);
467 CLIB_PAD_FROM_TO (0x42ac, 0x42b0);
468 u32 link_partner_ability[2];
469 CLIB_PAD_FROM_TO (0x42b8, 0x42d0);
471 u32 link_partner_next_page[2];
472 CLIB_PAD_FROM_TO (0x42dc, 0x42e0);
476 CLIB_PAD_FROM_TO (0x42f0, 0x4314);
478 CLIB_PAD_FROM_TO (0x4318, 0x4324);
480 CLIB_PAD_FROM_TO (0x4328, 0x4900);
487 CLIB_PAD_FROM_TO (0x4910, 0x4950);
490 u32 tx_packet_buffer_thresholds[8];
491 CLIB_PAD_FROM_TO (0x4970, 0x4980);
498 } dcb_tx_rate_scheduler;
499 CLIB_PAD_FROM_TO (0x4990, 0x4a80);
501 CLIB_PAD_FROM_TO (0x4a84, 0x4a88);
502 u32 tx_dma_tcp_flags_control[2];
503 CLIB_PAD_FROM_TO (0x4a90, 0x4b00);
505 CLIB_PAD_FROM_TO (0x4c00, 0x5000);
509 CLIB_PAD_FROM_TO (0x5004, 0x5008);
511 CLIB_PAD_FROM_TO (0x500c, 0x5010);
512 u32 management_vlan_tag[8];
513 u32 management_udp_tcp_ports[8];
514 CLIB_PAD_FROM_TO (0x5050, 0x5078);
517 CLIB_PAD_FROM_TO (0x507c, 0x5080);
523 CLIB_PAD_FROM_TO (0x5084, 0x5088);
529 CLIB_PAD_FROM_TO (0x508c, 0x5090);
535 CLIB_PAD_FROM_TO (0x5094, 0x5100);
537 CLIB_PAD_FROM_TO (0x5104, 0x5108);
539 CLIB_PAD_FROM_TO (0x510c, 0x5110);
541 CLIB_PAD_FROM_TO (0x5114, 0x5120);
543 CLIB_PAD_FROM_TO (0x5124, 0x5128);
553 u32 ethernet_type_queue_filter[8];
554 CLIB_PAD_FROM_TO (0x5148, 0x5160);
557 u32 management_decision_filters1[8];
558 u32 vf_vm_tx_switch_loopback_enable[2];
560 CLIB_PAD_FROM_TO (0x518c, 0x5190);
561 u32 management_ethernet_type_filters[4];
565 CLIB_PAD_FROM_TO (0x51ac, 0x51b0);
567 CLIB_PAD_FROM_TO (0x51b4, 0x51d8);
569 CLIB_PAD_FROM_TO (0x51dc, 0x51e0);
572 CLIB_PAD_FROM_TO (0x51ec, 0x5200);
575 u32 multicast_enable[128];
581 u32 rx_ethernet_address0[16][2];
583 CLIB_PAD_FROM_TO (0x5480, 0x5800);
585 CLIB_PAD_FROM_TO (0x5804, 0x5808);
587 CLIB_PAD_FROM_TO (0x580c, 0x5818);
589 CLIB_PAD_FROM_TO (0x581c, 0x5820);
592 CLIB_PAD_FROM_TO (0x5828, 0x5838);
594 CLIB_PAD_FROM_TO (0x583c, 0x5840);
595 u32 wake_up_ip4_address_table[4];
597 CLIB_PAD_FROM_TO (0x5854, 0x5880);
598 u32 wake_up_ip6_address_table[4];
602 u32 management_decision_filters[8];
604 u32 management_ip4_or_ip6_address_filters[4][4];
605 CLIB_PAD_FROM_TO (0x58f0, 0x5900);
607 CLIB_PAD_FROM_TO (0x5904, 0x5910);
608 u32 management_ethernet_address_filters[4][2];
609 CLIB_PAD_FROM_TO (0x5930, 0x5a00);
610 u32 wake_up_packet_memory[32];
611 CLIB_PAD_FROM_TO (0x5a80, 0x5c00);
612 u32 redirection_table_82598[32];
613 u32 rss_random_keys_82598[10];
614 CLIB_PAD_FROM_TO (0x5ca8, 0x6000);
618 u32 pf_vm_vlan_insert[64];
620 CLIB_PAD_FROM_TO (0x8104, 0x8110);
622 CLIB_PAD_FROM_TO (0x8118, 0x8120);
627 CLIB_PAD_FROM_TO (0x8124, 0x8200);
630 CLIB_PAD_FROM_TO (0x8224, 0x82e0);
631 u32 tx_strict_low_latency_queues[4];
632 CLIB_PAD_FROM_TO (0x82f0, 0x8600);
633 u32 tx_queue_stats_mapping_82599[32];
634 u32 tx_queue_packet_counts[32];
635 u32 tx_queue_byte_counts[32][2];
642 CLIB_PAD_FROM_TO (0x880c, 0x8810);
644 CLIB_PAD_FROM_TO (0x8814, 0x8900);
652 CLIB_PAD_FROM_TO (0x8918, 0x8a00);
666 CLIB_PAD_FROM_TO (0x8a50, 0x8c00);
675 u32 time_adjustment_offset[2];
678 CLIB_PAD_FROM_TO (0x8c34, 0x8c3c);
680 CLIB_PAD_FROM_TO (0x8c4c, 0x8d00);
687 CLIB_PAD_FROM_TO (0x8d08, 0x8e00);
699 CLIB_PAD_FROM_TO (0x8e34, 0x8f00);
712 CLIB_PAD_FROM_TO (0x8f84, 0x9000);
716 u32 flexible_filters[8][16][4];
717 CLIB_PAD_FROM_TO (0x9800, 0xa000);
726 u32 rx_ethernet_address1[128][2];
729 u32 rx_ethernet_address_pool_select[128][2];
730 CLIB_PAD_FROM_TO (0xaa00, 0xc800);
732 CLIB_PAD_FROM_TO (0xc804, 0xcc00);
735 u32 tx_packet_buffer_size[8];
737 CLIB_PAD_FROM_TO (0xcc20, 0xcd10);
739 CLIB_PAD_FROM_TO (0xcd14, 0xcd20);
740 u32 dcb_tx_packet_plane_t2_config[8];
741 u32 dcb_tx_packet_plane_t2_status[8];
742 CLIB_PAD_FROM_TO (0xcd60, 0xce00);
745 CLIB_PAD_FROM_TO (0xce04, 0xd000);
777 CLIB_PAD_FROM_TO (0xea00, 0xeb00);
780 u32 redirection_table_82599[32];
782 u32 rss_random_key_82599[10];
783 CLIB_PAD_FROM_TO (0xeba8, 0xec00);
788 u32 ethernet_type_queue_select[8];
789 CLIB_PAD_FROM_TO (0xec20, 0xec30);
791 CLIB_PAD_FROM_TO (0xec34, 0xec60);
793 CLIB_PAD_FROM_TO (0xec64, 0xec70);
795 CLIB_PAD_FROM_TO (0xec74, 0xec90);
797 CLIB_PAD_FROM_TO (0xec94, 0xed00);
802 CLIB_PAD_FROM_TO (0xed04, 0xed10);
804 CLIB_PAD_FROM_TO (0xed30, 0xee00);
819 CLIB_PAD_FROM_TO (0xee04, 0xee0c);
839 CLIB_PAD_FROM_TO (0xee30, 0xee3c);
848 CLIB_PAD_FROM_TO (0xee60, 0xee68);
861 CLIB_PAD_FROM_TO (0xee78, 0xf000);
868 u32 vlan_pool_filter_bitmap[128];
869 u32 dst_ethernet_address[128];
873 CLIB_PAD_FROM_TO (0xf650, 0x10010);
882 CLIB_PAD_FROM_TO (0x10018, 0x1001c);
884 CLIB_PAD_FROM_TO (0x10020, 0x10114);
888 CLIB_PAD_FROM_TO (0x10120, 0x1013c);
891 CLIB_PAD_FROM_TO (0x10144, 0x10148);
893 CLIB_PAD_FROM_TO (0x1014c, 0x10160);
895 CLIB_PAD_FROM_TO (0x10164, 0x10200);
897 CLIB_PAD_FROM_TO (0x10204, 0x11000);
902 CLIB_PAD_FROM_TO (0x11004, 0x11010);
915 CLIB_PAD_FROM_TO (0x11018, 0x11020);
916 u32 counters_clear_on_read[4];
923 CLIB_PAD_FROM_TO (0x11048, 0x11050);
924 u32 extended_control;
925 CLIB_PAD_FROM_TO (0x11054, 0x11064);
927 CLIB_PAD_FROM_TO (0x11068, 0x11070);
933 CLIB_PAD_FROM_TO (0x11078, 0x110b0);
939 CLIB_PAD_FROM_TO (0x110b4, 0x110b8);
941 CLIB_PAD_FROM_TO (0x110bc, 0x110c0);
943 CLIB_PAD_FROM_TO (0x110e0, 0x12300);
946 u32 interrupt_throttle1[128 - 24];
947 CLIB_PAD_FROM_TO (0x124a0, 0x14f00);
950 CLIB_PAD_FROM_TO (0x14f04, 0x14f10);
952 CLIB_PAD_FROM_TO (0x14f14, 0x15f14);
995 u32 queue_interrupt_index,
996 f64 inter_interrupt_interval_in_secs)
1002 ASSERT (queue_interrupt_index < 128);
1004 i32 i, mask = (1 << 9) - 1;
1008 i = i >= mask ? mask :
i;
1016 #define foreach_ixge_counter \ 1017 _ (0x40d0, rx_total_packets) \ 1018 _64 (0x40c0, rx_total_bytes) \ 1019 _ (0x41b0, rx_good_packets_before_filtering) \ 1020 _64 (0x41b4, rx_good_bytes_before_filtering) \ 1021 _ (0x2f50, rx_dma_good_packets) \ 1022 _64 (0x2f54, rx_dma_good_bytes) \ 1023 _ (0x2f5c, rx_dma_duplicated_good_packets) \ 1024 _64 (0x2f60, rx_dma_duplicated_good_bytes) \ 1025 _ (0x2f68, rx_dma_good_loopback_packets) \ 1026 _64 (0x2f6c, rx_dma_good_loopback_bytes) \ 1027 _ (0x2f74, rx_dma_good_duplicated_loopback_packets) \ 1028 _64 (0x2f78, rx_dma_good_duplicated_loopback_bytes) \ 1029 _ (0x4074, rx_good_packets) \ 1030 _64 (0x4088, rx_good_bytes) \ 1031 _ (0x407c, rx_multicast_packets) \ 1032 _ (0x4078, rx_broadcast_packets) \ 1033 _ (0x405c, rx_64_byte_packets) \ 1034 _ (0x4060, rx_65_127_byte_packets) \ 1035 _ (0x4064, rx_128_255_byte_packets) \ 1036 _ (0x4068, rx_256_511_byte_packets) \ 1037 _ (0x406c, rx_512_1023_byte_packets) \ 1038 _ (0x4070, rx_gt_1023_byte_packets) \ 1039 _ (0x4000, rx_crc_errors) \ 1040 _ (0x4120, rx_ip_checksum_errors) \ 1041 _ (0x4004, rx_illegal_symbol_errors) \ 1042 _ (0x4008, rx_error_symbol_errors) \ 1043 _ (0x4034, rx_mac_local_faults) \ 1044 _ (0x4038, rx_mac_remote_faults) \ 1045 _ (0x4040, rx_length_errors) \ 1046 _ (0x41a4, rx_xons) \ 1047 _ (0x41a8, rx_xoffs) \ 1048 _ (0x40a4, rx_undersize_packets) \ 1049 _ (0x40a8, rx_fragments) \ 1050 _ (0x40ac, rx_oversize_packets) \ 1051 _ (0x40b0, rx_jabbers) \ 1052 _ (0x40b4, rx_management_packets) \ 1053 _ (0x40b8, rx_management_drops) \ 1054 _ (0x3fa0, rx_missed_packets_pool_0) \ 1055 _ (0x40d4, tx_total_packets) \ 1056 _ (0x4080, tx_good_packets) \ 1057 _64 (0x4090, tx_good_bytes) \ 1058 _ (0x40f0, tx_multicast_packets) \ 1059 _ (0x40f4, tx_broadcast_packets) \ 1060 _ (0x87a0, tx_dma_good_packets) \ 1061 _64 (0x87a4, tx_dma_good_bytes) \ 1062 _ (0x40d8, tx_64_byte_packets) \ 1063 _ (0x40dc, tx_65_127_byte_packets) \ 1064 _ (0x40e0, tx_128_255_byte_packets) \ 1065 _ (0x40e4, tx_256_511_byte_packets) \ 1066 _ (0x40e8, tx_512_1023_byte_packets) \ 1067 _ (0x40ec, tx_gt_1023_byte_packets) \ 1068 _ (0x4010, tx_undersize_drops) \ 1069 _ (0x8780, switch_security_violation_packets) \ 1070 _ (0x5118, fc_crc_errors) \ 1071 _ (0x241c, fc_rx_drops) \ 1072 _ (0x2424, fc_last_error_count) \ 1073 _ (0x2428, fcoe_rx_packets) \ 1074 _ (0x242c, fcoe_rx_dwords) \ 1075 _ (0x8784, fcoe_tx_packets) \ 1076 _ (0x8788, fcoe_tx_dwords) \ 1077 _ (0x1030, queue_0_rx_count) \ 1078 _ (0x1430, queue_0_drop_count) \ 1079 _ (0x1070, queue_1_rx_count) \ 1080 _ (0x1470, queue_1_drop_count) \ 1081 _ (0x10b0, queue_2_rx_count) \ 1082 _ (0x14b0, queue_2_drop_count) \ 1083 _ (0x10f0, queue_3_rx_count) \ 1084 _ (0x14f0, queue_3_drop_count) \ 1085 _ (0x1130, queue_4_rx_count) \ 1086 _ (0x1530, queue_4_drop_count) \ 1087 _ (0x1170, queue_5_rx_count) \ 1088 _ (0x1570, queue_5_drop_count) \ 1089 _ (0x11b0, queue_6_rx_count) \ 1090 _ (0x15b0, queue_6_drop_count) \ 1091 _ (0x11f0, queue_7_rx_count) \ 1092 _ (0x15f0, queue_7_drop_count) \ 1093 _ (0x1230, queue_8_rx_count) \ 1094 _ (0x1630, queue_8_drop_count) \ 1095 _ (0x1270, queue_9_rx_count) \ 1096 _ (0x1270, queue_9_drop_count) 1103 #define _(a,f) IXGE_COUNTER_##f, 1104 #define _64(a,f) _(a,f) 1169 #define foreach_ixge_pci_device_id \ 1171 _ (82598_bx, 0x1508) \ 1172 _ (82598af_dual_port, 0x10c6) \ 1173 _ (82598af_single_port, 0x10c7) \ 1174 _ (82598at, 0x10c8) \ 1175 _ (82598at2, 0x150b) \ 1176 _ (82598eb_sfp_lom, 0x10db) \ 1177 _ (82598eb_cx4, 0x10dd) \ 1178 _ (82598_cx4_dual_port, 0x10ec) \ 1179 _ (82598_da_dual_port, 0x10f1) \ 1180 _ (82598_sr_dual_port_em, 0x10e1) \ 1181 _ (82598eb_xf_lr, 0x10f4) \ 1182 _ (82599_kx4, 0x10f7) \ 1183 _ (82599_kx4_mezz, 0x1514) \ 1184 _ (82599_kr, 0x1517) \ 1185 _ (82599_combo_backplane, 0x10f8) \ 1186 _ (82599_cx4, 0x10f9) \ 1187 _ (82599_sfp, 0x10fb) \ 1188 _ (82599_backplane_fcoe, 0x152a) \ 1189 _ (82599_sfp_fcoe, 0x1529) \ 1190 _ (82599_sfp_em, 0x1507) \ 1191 _ (82599_xaui_lom, 0x10fc) \ 1192 _ (82599_t3_lom, 0x151c) \ 1197 #define _(f,n) IXGE_##f = n,
u32 tx_dma_tcp_max_alloc_size_requests
u32 dcb_packet_plane_control
sll srl srl sll sra u16x4 i
u32 auto_negotiation_tx_next_page
ixge_rx_to_hw_descriptor_t rx_to_hw
u32 enable_write_1_to_set
u32 link_status_at_last_link_change
u32 interrupt_throttle1[128-24]
u32 saved_start_of_packet_buffer_index
u32 * descriptor_buffer_indices
u32 tx_manageability_tc_mapping
u32 management_filter_control
void ixge_set_next_node(ixge_rx_next_t, char *)
u32 rx_queue_stats_control
u32 *volatile head_index_write_back
static void ixge_throttle_queue_interrupt(ixge_regs_t *r, u32 queue_interrupt_index, f64 inter_interrupt_interval_in_secs)
u32 per_interface_next_index
u32 rx_dma_descriptor_cache_config
u32 tx_priority_to_traffic_class
u32 tx_flow_control_status
u32 enable_write_1_to_clear
struct _vnet_device_class vnet_device_class_t
u32 * tx_buffers_pending_free
vlib_pci_dev_handle_t pci_dev_handle
u32 rx_coallesce_data_buffer_control
u32 manageability_control
u32 pcie_interrupt_status
vnet_device_class_t ixge_device_class
u32 pause_and_pace_control
#define foreach_ixge_pci_device_id
u32 saved_last_buffer_index
u32 tx_dcb_descriptor_plane_t1_status
u32 wake_up_ip4_address_valid
f64 time_last_stats_update
struct ixge_regs_t::@331 interrupt
u32 rx_priority_to_traffic_class
u32 immediate_interrupt_rx_vlan_priority
#define foreach_ixge_counter
u32 pcie_interrupt_enable
u32 link_sec_software_firmware_interface
u32 auto_negotiation_link_partner_next_page
u32 vlib_pci_dev_handle_t
u32 tx_dcb_descriptor_plane_queue_select
u32 saved_start_of_packet_next_index
u32 dca_requester_id_information
u32 multiple_tx_queues_command
int physmem_region_allocated
u8 checksum_insert_offset
u32 software_firmware_sync
u32 auto_negotiation_control2
u32 flow_control_refresh_threshold
u32 status_write_1_to_set
u32 n_descriptors_done_total
vlib_node_runtime_t * node
u32 rx_timestamp_attributes_lo
u32 extended_vlan_ether_type
ixge_pci_device_id_t device_id
ixge_descriptor_t * descriptors
u32 n_descriptors_done_this_call
u32 auto_negotiation_control
u32 wake_up_filter_control
u32 multiple_rx_queue_command_82598
u32 pf_dma_tx_switch_control
u32 rx_timestamp_attributes_hi
ip6_address_t src_address
ixge_tx_descriptor_t tx_descriptor_template_mask
u32 * replenish_buffer_indices
u32 rss_queues_per_traffic_class
u32 management_control_to_host
static word flt_round_nearest(f64 x)
u32 tx_dcb_descriptor_plane_t1_config
u32 n_descriptors_per_cache_line
vlib_physmem_region_index_t physmem_region
u32 wake_up_packet_length
u16 n_packet_bytes_this_descriptor
u32 status_auto_clear_enable
u32 rx_packet_buffer_flush_detect
u32 status_write_1_to_clear
u8 vlib_physmem_region_index_t
ip4_address_t src_address
ixge_rx_from_hw_descriptor_t rx_from_hw
u32 syn_packet_queue_filter