FD.io VPP  v18.04-17-g3a0d853
Vector Packet Processing
pci_config_type1_regs_t Struct Reference
+ Collaboration diagram for pci_config_type1_regs_t:

Data Fields

pci_config_header_t header
 
u32 base_address [2]
 
u8 primary_bus
 
u8 secondary_bus
 
u8 subordinate_bus
 
u8 secondary_bus_latency_timer
 
u8 io_base
 
u8 io_limit
 
u16 secondary_status
 
u16 memory_base
 
u16 memory_limit
 
u16 prefetchable_memory_base
 
u16 prefetchable_memory_limit
 
u32 prefetchable_memory_base_upper_32bits
 
u32 prefetchable_memory_limit_upper_32bits
 
u16 io_base_upper_16bits
 
u16 io_limit_upper_16bits
 
u8 capability_list_offset
 
u8 pad_0x35 [(0x37)-(0x35)]
 Padding. More...
 
u32 rom_address
 
u8 pad_0x3c [(0x3e)-(0x3c)]
 Padding. More...
 
u16 bridge_control
 
u8 capability_data [0]
 

Detailed Description

Definition at line 296 of file pci_config.h.

Field Documentation

u32 pci_config_type1_regs_t::base_address[2]

Definition at line 300 of file pci_config.h.

u16 pci_config_type1_regs_t::bridge_control

Definition at line 340 of file pci_config.h.

u8 pci_config_type1_regs_t::capability_data[0]

Definition at line 349 of file pci_config.h.

u8 pci_config_type1_regs_t::capability_list_offset

Definition at line 334 of file pci_config.h.

pci_config_header_t pci_config_type1_regs_t::header

Definition at line 298 of file pci_config.h.

u8 pci_config_type1_regs_t::io_base

Definition at line 312 of file pci_config.h.

u16 pci_config_type1_regs_t::io_base_upper_16bits

Definition at line 330 of file pci_config.h.

u8 pci_config_type1_regs_t::io_limit

Definition at line 312 of file pci_config.h.

u16 pci_config_type1_regs_t::io_limit_upper_16bits

Definition at line 331 of file pci_config.h.

u16 pci_config_type1_regs_t::memory_base

Definition at line 318 of file pci_config.h.

u16 pci_config_type1_regs_t::memory_limit

Definition at line 318 of file pci_config.h.

u8 pci_config_type1_regs_t::pad_0x35[(0x37)-(0x35)]

Padding.

Definition at line 335 of file pci_config.h.

u8 pci_config_type1_regs_t::pad_0x3c[(0x3e)-(0x3c)]

Padding.

Definition at line 338 of file pci_config.h.

u16 pci_config_type1_regs_t::prefetchable_memory_base

Definition at line 322 of file pci_config.h.

u32 pci_config_type1_regs_t::prefetchable_memory_base_upper_32bits

Definition at line 328 of file pci_config.h.

u16 pci_config_type1_regs_t::prefetchable_memory_limit

Definition at line 322 of file pci_config.h.

u32 pci_config_type1_regs_t::prefetchable_memory_limit_upper_32bits

Definition at line 329 of file pci_config.h.

u8 pci_config_type1_regs_t::primary_bus

Definition at line 303 of file pci_config.h.

u32 pci_config_type1_regs_t::rom_address

Definition at line 337 of file pci_config.h.

u8 pci_config_type1_regs_t::secondary_bus

Definition at line 304 of file pci_config.h.

u8 pci_config_type1_regs_t::secondary_bus_latency_timer

Definition at line 309 of file pci_config.h.

u16 pci_config_type1_regs_t::secondary_status

Definition at line 315 of file pci_config.h.

u8 pci_config_type1_regs_t::subordinate_bus

Definition at line 307 of file pci_config.h.


The documentation for this struct was generated from the following file: