50 struct rte_eth_dev_info dev_info;
51 struct rte_pci_device *pci_dev;
56 if (hw_if_index == (
u32) ~ 0)
71 rte_eth_dev_info_get ((*xd)->port_id, &dev_info);
77 vlib_pci_addr_t pci_addr;
79 pci_addr.domain = pci_dev->addr.domain;
80 pci_addr.bus = pci_dev->addr.bus;
81 pci_addr.slot = pci_dev->addr.devid;
82 pci_addr.function = pci_dev->addr.function;
110 unsigned count = rte_mempool_avail_count (rmp);
111 unsigned free_count = rte_mempool_in_use_count (rmp);
114 "name=\"%s\" available = %7d allocated = %7d total = %7d\n",
116 (
u32) (count + free_count));
137 .path =
"show dpdk buffer",
138 .short_help =
"show dpdk buffer",
155 err =
clib_sysfs_read (
"/proc/sys/fs/pipe-max-size",
"%u", &pipe_max_size);
160 if (pipe (fds) == -1)
164 #define F_SETPIPE_SZ (1024 + 7) 173 if (fcntl (fds[0], F_SETFL, O_NONBLOCK) == -1)
179 if ((f = fdopen (fds[1],
"a")) == 0)
185 rte_dump_physmem_layout (f);
194 n = read (fds[0], s + len, n_try);
195 if (n < 0 && errno != EAGAIN)
200 _vec_len (s) = len + (n < 0 ? 0 : n);
222 .path =
"show dpdk physmem",
223 .short_help =
"show dpdk physmem",
233 static u32 *allocated_buffers;
240 if (
unformat (input,
"allocate %d", &n_alloc))
242 else if (
unformat (input,
"free %d", &n_free))
250 if (
vec_len (allocated_buffers) < n_free)
252 n_free,
vec_len (allocated_buffers));
254 first =
vec_len (allocated_buffers) - n_free;
256 _vec_len (allocated_buffers) =
first;
260 first =
vec_len (allocated_buffers);
262 vec_len (allocated_buffers) + n_alloc - 1);
266 _vec_len (allocated_buffers) = first + actual_alloc;
268 if (actual_alloc < n_alloc)
276 if (allocated_buffers &&
vec_len (allocated_buffers) == 0)
310 .path =
"test dpdk buffer",
311 .short_help =
"test dpdk buffer [allocate <nn>] [free <nn>]",
325 u32 hw_if_index = (
u32) ~ 0;
326 u32 nb_rx_desc = (
u32) ~ 0;
327 u32 nb_tx_desc = (
u32) ~ 0;
339 else if (
unformat (line_input,
"tx %d", &nb_tx_desc))
341 else if (
unformat (line_input,
"rx %d", &nb_rx_desc))
351 if (hw_if_index == (
u32) ~ 0)
360 if ((xd->
flags & DPDK_DEVICE_FLAG_PMD) == 0)
364 "number of descriptors can be set only for " 369 if ((nb_rx_desc == (
u32) ~ 0 || nb_rx_desc == xd->
nb_rx_desc) &&
376 if (nb_rx_desc != (
u32) ~ 0)
379 if (nb_tx_desc != (
u32) ~ 0)
405 .path =
"set dpdk interface descriptors",
406 .short_help =
"set dpdk interface descriptors <interface> [rx <nn>] [tx <nn>]",
413 dpdk_device_queue_sort (
void *a1,
void *a2)
477 .path =
"show dpdk interface hqos placement",
478 .short_help =
"show dpdk interface hqos placement",
479 .function = show_dpdk_if_hqos_placement,
492 u32 hw_if_index = (
u32) ~ 0;
506 else if (
unformat (line_input,
"thread %d", &cpu))
516 if (hw_if_index == (
u32) ~ 0)
519 if (cpu < dm->hqos_cpu_first_index ||
545 dpdk_device_queue_sort);
548 dpdk_device_queue_sort);
582 .path =
"set dpdk interface hqos placement",
583 .short_help =
"set dpdk interface hqos placement <interface> thread <n>",
584 .function = set_dpdk_if_hqos_placement,
596 u32 hw_if_index = (
u32) ~ 0;
597 u32 subport_id = (
u32) ~ 0;
599 u32 profile_id = (
u32) ~ 0;
612 else if (
unformat (line_input,
"subport %d", &subport_id))
614 else if (
unformat (line_input,
"pipe %d", &pipe_id))
616 else if (
unformat (line_input,
"profile %d", &profile_id))
626 if (hw_if_index == (
u32) ~ 0)
636 rte_sched_pipe_config (xd->
hqos_ht->
hqos, subport_id, pipe_id,
669 .path =
"set dpdk interface hqos pipe",
670 .short_help =
"set dpdk interface hqos pipe <interface> subport <subport_id> pipe <pipe_id> " 671 "profile <profile_id>",
672 .function = set_dpdk_if_hqos_pipe,
683 u32 hw_if_index = (
u32) ~ 0;
684 u32 subport_id = (
u32) ~ 0;
685 struct rte_sched_subport_params p;
690 u32 tc_rate[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE] =
692 u32 tc_period = (
u32) ~ 0;
704 else if (
unformat (line_input,
"subport %d", &subport_id))
706 else if (
unformat (line_input,
"rate %d", &tb_rate))
708 else if (
unformat (line_input,
"bktsize %d", &tb_size))
710 else if (
unformat (line_input,
"tc0 %d", &tc_rate[0]))
712 else if (
unformat (line_input,
"tc1 %d", &tc_rate[1]))
714 else if (
unformat (line_input,
"tc2 %d", &tc_rate[2]))
716 else if (
unformat (line_input,
"tc3 %d", &tc_rate[3]))
718 else if (
unformat (line_input,
"period %d", &tc_period))
728 error = get_hqos (hw_if_index, subport_id, &xd, &devconf);
733 memcpy (&p, &devconf->
hqos.
subport[subport_id], sizeof (p));
736 if (tb_rate != (
u32) ~ 0)
739 p.tc_rate[0] = tb_rate;
740 p.tc_rate[1] = tb_rate;
741 p.tc_rate[2] = tb_rate;
742 p.tc_rate[3] = tb_rate;
744 if (tb_size != (
u32) ~ 0)
748 if (tc_rate[0] != (
u32) ~ 0)
750 p.tc_rate[0] = tc_rate[0];
752 if (tc_rate[1] != (
u32) ~ 0)
754 p.tc_rate[1] = tc_rate[1];
756 if (tc_rate[2] != (
u32) ~ 0)
758 p.tc_rate[2] = tc_rate[2];
760 if (tc_rate[3] != (
u32) ~ 0)
762 p.tc_rate[3] = tc_rate[3];
764 if (tc_period != (
u32) ~ 0)
766 p.tc_period = tc_period;
770 rv = rte_sched_subport_config (xd->
hqos_ht->
hqos, subport_id, &p);
779 memcpy (&devconf->
hqos.
subport[subport_id], &p, sizeof (p));
806 .path =
"set dpdk interface hqos subport",
807 .short_help =
"set dpdk interface hqos subport <interface> subport <subport_id> " 808 "[rate <n>] [bktsize <n>] [tc0 <n>] [tc1 <n>] [tc2 <n>] [tc3 <n>] " 810 .function = set_dpdk_if_hqos_subport,
823 u32 hw_if_index = (
u32) ~ 0;
839 else if (
unformat (line_input,
"entry %d", &entry))
841 else if (
unformat (line_input,
"tc %d", &tc))
843 else if (
unformat (line_input,
"queue %d", &queue))
853 if (hw_if_index == (
u32) ~ 0)
863 if (tc >= RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE)
868 if (queue >= RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS)
888 int worker_thread_count = tr->
count;
890 val = tc * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
891 for (i = 0; i < worker_thread_count; i++)
923 .path =
"set dpdk interface hqos tctbl",
924 .short_help =
"set dpdk interface hqos tctbl <interface> entry <map_val> tc <tc_id> queue <queue_id>",
925 .function = set_dpdk_if_hqos_tctbl,
939 struct rte_eth_dev_info dev_info;
940 struct rte_pci_device *pci_dev;
944 u32 hw_if_index = (
u32) ~ 0;
954 int worker_thread_count = tr->
count;
962 u32 n_subports_per_port, n_pipes_per_subport, tctbl_size;
976 else if (
unformat (line_input,
"id subport"))
978 else if (
unformat (line_input,
"id pipe"))
980 else if (
unformat (line_input,
"id tc"))
982 else if (
unformat (line_input,
"id %d", &
id))
984 else if (
unformat (line_input,
"offset %d", &offset))
986 else if (
unformat (line_input,
"mask %llx", &mask))
997 if (hw_if_index == (
u32) ~ 0)
1006 rte_eth_dev_info_get (xd->
port_id, &dev_info);
1012 vlib_pci_addr_t pci_addr;
1014 pci_addr.domain = pci_dev->addr.domain;
1015 pci_addr.bus = pci_dev->addr.bus;
1016 pci_addr.slot = pci_dev->addr.devid;
1017 pci_addr.function = pci_dev->addr.function;
1034 n_subports_per_port = devconf->
hqos.
port.n_subports_per_port;
1035 n_pipes_per_subport = devconf->
hqos.
port.n_pipes_per_subport;
1051 "(n_subports_per_port = %u)",
1052 n_subports_per_port);
1060 "(n_pipes_per_subport = %u)",
1061 n_pipes_per_subport);
1070 "(TC table size = %u)", tctbl_size);
1076 for (i = 0; i < worker_thread_count; i++)
1146 .path =
"set dpdk interface hqos pktfield",
1147 .short_help =
"set dpdk interface hqos pktfield <interface> id subport|pipe|tc offset <n> " 1149 .function = set_dpdk_if_hqos_pktfield,
1166 u32 hw_if_index = (
u32) ~ 0;
1167 u32 profile_id, subport_id,
i;
1168 struct rte_eth_dev_info dev_info;
1169 struct rte_pci_device *pci_dev;
1192 if (hw_if_index == (
u32) ~ 0)
1201 rte_eth_dev_info_get (xd->
port_id, &dev_info);
1207 vlib_pci_addr_t pci_addr;
1209 pci_addr.domain = pci_dev->addr.domain;
1210 pci_addr.bus = pci_dev->addr.bus;
1211 pci_addr.slot = pci_dev->addr.devid;
1212 pci_addr.function = pci_dev->addr.function;
1241 cfg = &devconf->
hqos;
1254 " Packet field 0: slab position = %4u, slab bitmask = 0x%016llx (subport)",
1257 " Packet field 1: slab position = %4u, slab bitmask = 0x%016llx (pipe)",
1260 " Packet field 2: slab position = %4u, slab bitmask = 0x%016llx (tc)",
1263 " Packet field 2 tc translation table: ([Mapped Value Range]: tc/queue tc/queue ...)");
1266 "%u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u",
1267 tctbl[0] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1268 tctbl[0] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1269 tctbl[1] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1270 tctbl[1] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1271 tctbl[2] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1272 tctbl[2] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1273 tctbl[3] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1274 tctbl[3] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1275 tctbl[4] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1276 tctbl[4] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1277 tctbl[5] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1278 tctbl[5] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1279 tctbl[6] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1280 tctbl[6] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1281 tctbl[7] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1282 tctbl[7] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1283 tctbl[8] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1284 tctbl[8] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1285 tctbl[9] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1286 tctbl[9] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1287 tctbl[10] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1288 tctbl[10] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1289 tctbl[11] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1290 tctbl[11] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1291 tctbl[12] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1292 tctbl[12] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1293 tctbl[13] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1294 tctbl[13] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1295 tctbl[14] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1296 tctbl[14] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1297 tctbl[15] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1298 tctbl[15] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);
1301 "%u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u",
1302 tctbl[16] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1303 tctbl[16] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1304 tctbl[17] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1305 tctbl[17] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1306 tctbl[18] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1307 tctbl[18] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1308 tctbl[19] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1309 tctbl[19] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1310 tctbl[20] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1311 tctbl[20] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1312 tctbl[21] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1313 tctbl[21] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1314 tctbl[22] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1315 tctbl[22] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1316 tctbl[23] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1317 tctbl[23] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1318 tctbl[24] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1319 tctbl[24] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1320 tctbl[25] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1321 tctbl[25] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1322 tctbl[26] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1323 tctbl[26] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1324 tctbl[27] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1325 tctbl[27] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1326 tctbl[28] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1327 tctbl[28] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1328 tctbl[29] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1329 tctbl[29] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1330 tctbl[30] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1331 tctbl[30] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1332 tctbl[31] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1333 tctbl[31] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);
1336 "%u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u",
1337 tctbl[32] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1338 tctbl[32] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1339 tctbl[33] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1340 tctbl[33] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1341 tctbl[34] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1342 tctbl[34] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1343 tctbl[35] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1344 tctbl[35] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1345 tctbl[36] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1346 tctbl[36] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1347 tctbl[37] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1348 tctbl[37] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1349 tctbl[38] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1350 tctbl[38] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1351 tctbl[39] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1352 tctbl[39] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1353 tctbl[40] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1354 tctbl[40] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1355 tctbl[41] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1356 tctbl[41] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1357 tctbl[42] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1358 tctbl[42] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1359 tctbl[43] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1360 tctbl[43] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1361 tctbl[44] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1362 tctbl[44] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1363 tctbl[45] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1364 tctbl[45] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1365 tctbl[46] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1366 tctbl[46] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1367 tctbl[47] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1368 tctbl[47] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);
1371 "%u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u %u/%u",
1372 tctbl[48] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1373 tctbl[48] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1374 tctbl[49] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1375 tctbl[49] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1376 tctbl[50] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1377 tctbl[50] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1378 tctbl[51] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1379 tctbl[51] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1380 tctbl[52] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1381 tctbl[52] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1382 tctbl[53] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1383 tctbl[53] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1384 tctbl[54] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1385 tctbl[54] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1386 tctbl[55] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1387 tctbl[55] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1388 tctbl[56] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1389 tctbl[56] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1390 tctbl[57] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1391 tctbl[57] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1392 tctbl[58] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1393 tctbl[58] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1394 tctbl[59] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1395 tctbl[59] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1396 tctbl[60] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1397 tctbl[60] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1398 tctbl[61] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1399 tctbl[61] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1400 tctbl[62] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1401 tctbl[62] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1402 tctbl[63] / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS,
1403 tctbl[63] % RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);
1408 cfg->
port.frame_overhead);
1410 cfg->
port.n_subports_per_port);
1412 cfg->
port.n_pipes_per_subport);
1414 " Packet queue size: TC0 = %u, TC1 = %u, TC2 = %u, TC3 = %u packets",
1415 cfg->
port.qsize[0], cfg->
port.qsize[1], cfg->
port.qsize[2],
1416 cfg->
port.qsize[3]);
1418 cfg->
port.n_pipe_profiles);
1420 for (subport_id = 0; subport_id <
vec_len (cfg->
subport); subport_id++)
1424 cfg->
subport[subport_id].tb_rate);
1426 cfg->
subport[subport_id].tb_size);
1428 " Traffic class rate: TC0 = %u, TC1 = %u, TC2 = %u, TC3 = %u bytes/second",
1429 cfg->
subport[subport_id].tc_rate[0],
1430 cfg->
subport[subport_id].tc_rate[1],
1431 cfg->
subport[subport_id].tc_rate[2],
1432 cfg->
subport[subport_id].tc_rate[3]);
1434 cfg->
subport[subport_id].tc_period);
1437 for (profile_id = 0; profile_id <
vec_len (cfg->
pipe); profile_id++)
1441 cfg->
pipe[profile_id].tb_rate);
1443 cfg->
pipe[profile_id].tb_size);
1445 " Traffic class rate: TC0 = %u, TC1 = %u, TC2 = %u, TC3 = %u bytes/second",
1446 cfg->
pipe[profile_id].tc_rate[0],
1447 cfg->
pipe[profile_id].tc_rate[1],
1448 cfg->
pipe[profile_id].tc_rate[2],
1449 cfg->
pipe[profile_id].tc_rate[3]);
1451 cfg->
pipe[profile_id].tc_period);
1452 #ifdef RTE_SCHED_SUBPORT_TC_OV 1454 cfg->
pipe[profile_id].tc_ov_weight);
1457 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
1460 " TC%u WRR weights: Q0 = %u, Q1 = %u, Q2 = %u, Q3 = %u",
1461 i, cfg->
pipe[profile_id].wrr_weights[i * 4],
1462 cfg->
pipe[profile_id].wrr_weights[i * 4 + 1],
1463 cfg->
pipe[profile_id].wrr_weights[i * 4 + 2],
1464 cfg->
pipe[profile_id].wrr_weights[i * 4 + 3]);
1468 #ifdef RTE_SCHED_RED 1470 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
1473 cfg->
port.red_params[i][e_RTE_METER_GREEN].min_th,
1474 cfg->
port.red_params[i][e_RTE_METER_YELLOW].min_th,
1475 cfg->
port.red_params[i][e_RTE_METER_RED].min_th);
1478 cfg->
port.red_params[i][e_RTE_METER_GREEN].max_th,
1479 cfg->
port.red_params[i][e_RTE_METER_YELLOW].max_th,
1480 cfg->
port.red_params[i][e_RTE_METER_RED].max_th);
1483 " TC%u inverted probability: G = %u, Y = %u, R = %u",
1484 i, cfg->
port.red_params[i][e_RTE_METER_GREEN].maxp_inv,
1485 cfg->
port.red_params[i][e_RTE_METER_YELLOW].maxp_inv,
1486 cfg->
port.red_params[i][e_RTE_METER_RED].maxp_inv);
1489 cfg->
port.red_params[i][e_RTE_METER_GREEN].wq_log2,
1490 cfg->
port.red_params[i][e_RTE_METER_YELLOW].wq_log2,
1491 cfg->
port.red_params[i][e_RTE_METER_RED].wq_log2);
1546 .path =
"show dpdk interface hqos",
1547 .short_help =
"show dpdk interface hqos <interface>",
1548 .function = show_dpdk_if_hqos,
1559 #ifdef RTE_SCHED_COLLECT_STATS 1561 u32 hw_if_index = (
u32) ~ 0;
1569 struct rte_eth_dev_info dev_info;
1570 struct rte_pci_device *pci_dev;
1573 struct rte_sched_queue_stats stats;
1586 else if (
unformat (line_input,
"subport %d", &subport))
1589 else if (
unformat (line_input,
"pipe %d", &pipe))
1592 else if (
unformat (line_input,
"tc %d", &tc))
1595 else if (
unformat (line_input,
"tc_q %d", &tc_q))
1606 if (hw_if_index == (
u32) ~ 0)
1615 rte_eth_dev_info_get (xd->
port_id, &dev_info);
1621 vlib_pci_addr_t pci_addr;
1623 pci_addr.domain = pci_dev->addr.domain;
1624 pci_addr.bus = pci_dev->addr.bus;
1625 pci_addr.slot = pci_dev->addr.devid;
1626 pci_addr.function = pci_dev->addr.function;
1647 qindex = subport * devconf->
hqos.
port.n_pipes_per_subport + pipe;
1648 qindex = qindex * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + tc;
1649 qindex = qindex * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + tc_q;
1651 if (rte_sched_queue_read_stats (xd->
hqos_ht->
hqos, qindex, &stats, &qlen) !=
1660 vlib_cli_output (vm,
"%=24s%=16d",
"Packets dropped", stats.n_pkts_dropped);
1661 #ifdef RTE_SCHED_RED 1663 stats.n_pkts_red_dropped);
1666 vlib_cli_output (vm,
"%=24s%=16d",
"Bytes dropped", stats.n_bytes_dropped);
1706 .path =
"show dpdk hqos queue",
1707 .short_help =
"show dpdk hqos queue <interface> subport <subport_id> pipe <pipe_id> tc <tc_id> tc_q <queue_id>",
1708 .function = show_dpdk_hqos_queue_stats,
1718 #define _(a,b,c) vlib_cli_output (vm, "%-25s " b, a ":", c); 1719 _(
"DPDK Version",
"%s", rte_version ());
1738 .path =
"show dpdk version",
1739 .short_help =
"show dpdk version",
unformat_function_t unformat_vnet_hw_interface
#define vec_validate(V, I)
Make sure vector is long enough for given index (no header, unspecified alignment) ...
static void vlib_buffer_free(vlib_main_t *vm, u32 *buffers, u32 n_buffers)
Free buffers Frees the entire buffer chain for each buffer.
static clib_error_t * set_dpdk_if_desc(vlib_main_t *vm, unformat_input_t *input, vlib_cli_command_t *cmd)
struct rte_pci_device * dpdk_get_pci_device(const struct rte_eth_dev_info *info)
static vnet_hw_interface_t * vnet_get_hw_interface(vnet_main_t *vnm, u32 hw_if_index)
dpdk_device_and_queue_t ** devices_by_hqos_cpu
#define vec_add2(V, P, N)
Add N elements to end of vector V, return pointer to new elements in P.
struct rte_sched_port_params port
vlib_buffer_main_t * buffer_main
struct rte_sched_port * hqos
dpdk_device_config_hqos_t hqos
#define count_trailing_zeros(x)
static clib_error_t * show_dpdk_buffer(vlib_main_t *vm, unformat_input_t *input, vlib_cli_command_t *cmd)
struct rte_sched_pipe_params * pipe
#define VLIB_INIT_FUNCTION(x)
dpdk_config_main_t dpdk_config_main
dpdk_device_config_t default_devconf
#define vec_elt_at_index(v, i)
Get vector value at index i checking that i is in bounds.
#define clib_error_return(e, args...)
#define vec_resize(V, N)
Resize a vector (no header, unspecified alignment) Add N elements to end of given vector V...
void dpdk_device_setup(dpdk_device_t *xd)
static clib_error_t * test_dpdk_buffer(vlib_main_t *vm, unformat_input_t *input, vlib_cli_command_t *cmd)
dpdk_device_hqos_per_worker_thread_t * hqos_wt
static heap_elt_t * first(heap_header_t *h)
void dpdk_cli_reference(void)
vlib_worker_thread_t * vlib_worker_threads
#define pool_elt_at_index(p, i)
Returns pointer to element at given index.
#define clib_error_return_unix(e, args...)
vlib_buffer_pool_t * buffer_pools
#define vec_del1(v, i)
Delete the element at index I.
clib_error_t * clib_sysfs_read(char *file_name, char *fmt,...)
static clib_error_t * show_dpdk_physmem(vlib_main_t *vm, unformat_input_t *input, vlib_cli_command_t *cmd)
int dpdk_hqos_validate_mask(u64 mask, u32 n)
#define vec_free(V)
Free vector's memory (no header).
dpdk_device_config_t * dev_confs
format_function_t format_dpdk_device_errors
#define VLIB_CLI_COMMAND(x,...)
dpdk_device_hqos_per_hqos_thread_t * hqos_ht
uword * thread_registrations_by_name
clib_error_t * dpdk_cli_init(vlib_main_t *vm)
dpdk_portid_t device_index
template key/value backing page structure
#define vec_len(v)
Number of elements in vector (rvalue-only, NULL tolerant)
#define vec_sort_with_function(vec, f)
Sort a vector using the supplied element comparison function.
#define hash_get_mem(h, key)
struct clib_bihash_value offset
template key/value backing page structure
static vlib_thread_main_t * vlib_get_thread_main()
struct rte_sched_subport_params * subport
#define vec_foreach(var, vec)
Vector iterator.
static clib_error_t * show_dpdk_version_command_fn(vlib_main_t *vm, unformat_input_t *input, vlib_cli_command_t *cmd)
struct rte_mempool ** dpdk_mempool_by_buffer_pool_index
static u32 vlib_buffer_alloc(vlib_main_t *vm, u32 *buffers, u32 n_buffers)
Allocate buffers into supplied array.
void vlib_cli_output(vlib_main_t *vm, char *fmt,...)
uword * device_config_index_by_pci_addr
CLIB vectors are ubiquitous dynamically resized arrays with by user defined "headers".
dpdk_config_main_t * conf