40 #ifndef included_vlib_pci_config_h 41 #define included_vlib_pci_config_h 168 #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000 169 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041 181 #define PCI_COMMAND_IO (1 << 0) 182 #define PCI_COMMAND_MEMORY (1 << 1) 183 #define PCI_COMMAND_BUS_MASTER (1 << 2) 184 #define PCI_COMMAND_SPECIAL (1 << 3) 185 #define PCI_COMMAND_WRITE_INVALIDATE (1 << 4) 186 #define PCI_COMMAND_VGA_PALETTE_SNOOP (1 << 5) 187 #define PCI_COMMAND_PARITY (1 << 6) 188 #define PCI_COMMAND_WAIT (1 << 7) 189 #define PCI_COMMAND_SERR (1 << 8) 190 #define PCI_COMMAND_BACK_TO_BACK_WRITE (1 << 9) 191 #define PCI_COMMAND_INTX_DISABLE (1 << 10) 194 #define PCI_STATUS_INTX_PENDING (1 << 3) 195 #define PCI_STATUS_CAPABILITY_LIST (1 << 4) 196 #define PCI_STATUS_66MHZ (1 << 5) 197 #define PCI_STATUS_UDF (1 << 6) 198 #define PCI_STATUS_BACK_TO_BACK_WRITE (1 << 7) 199 #define PCI_STATUS_PARITY_ERROR (1 << 8) 200 #define PCI_STATUS_DEVSEL_GET(x) ((x >> 9) & 3) 201 #define PCI_STATUS_DEVSEL_FAST (0 << 9) 202 #define PCI_STATUS_DEVSEL_MEDIUM (1 << 9) 203 #define PCI_STATUS_DEVSEL_SLOW (2 << 9) 204 #define PCI_STATUS_SIG_TARGET_ABORT (1 << 11) 205 #define PCI_STATUS_REC_TARGET_ABORT (1 << 12) 206 #define PCI_STATUS_REC_MASTER_ABORT (1 << 13) 207 #define PCI_STATUS_SIG_SYSTEM_ERROR (1 << 14) 208 #define PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15) 219 #define PCI_HEADER_TYPE_NORMAL 0 220 #define PCI_HEADER_TYPE_BRIDGE 1 221 #define PCI_HEADER_TYPE_CARDBUS 2 224 #define PCI_BIST_CODE_MASK 0x0f 225 #define PCI_BIST_START 0x40 226 #define PCI_BIST_CAPABLE 0x80 235 #define _(f,t) r->f = clib_byte_swap_##t (r->f) 240 _(device_class,
u16);
263 #define PCI_ROM_ADDRESS 0x30 264 #define PCI_ROM_ADDRESS_ENABLE 0x01 265 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 268 CLIB_PAD_FROM_TO (0x35, 0x3c);
275 u8 capability_data[0];
285 #define _(f,t) r->f = clib_byte_swap_##t (r->f) 287 _(base_address[i],
u32);
289 _(subsystem_vendor_id,
u16);
290 _(subsystem_id,
u16);
319 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 320 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 323 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 324 #define PCI_PREF_RANGE_TYPE_32 0x00 325 #define PCI_PREF_RANGE_TYPE_64 0x01 326 #define PCI_PREF_RANGE_MASK (~0x0fUL) 335 CLIB_PAD_FROM_TO (0x35, 0x37);
338 CLIB_PAD_FROM_TO (0x3c, 0x3e);
341 #define PCI_BRIDGE_CTL_PARITY 0x01 342 #define PCI_BRIDGE_CTL_SERR 0x02 343 #define PCI_BRIDGE_CTL_NO_ISA 0x04 344 #define PCI_BRIDGE_CTL_VGA 0x08 345 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 346 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 347 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 349 u8 capability_data[0];
359 #define _(f,t) r->f = clib_byte_swap_##t (r->f) 361 _(base_address[i],
u32);
362 _(secondary_status,
u16);
364 _(memory_limit,
u16);
365 _(prefetchable_memory_base,
u16);
366 _(prefetchable_memory_limit,
u16);
367 _(prefetchable_memory_base_upper_32bits,
u32);
368 _(prefetchable_memory_limit_upper_32bits,
u32);
369 _(io_base_upper_16bits,
u16);
370 _(io_limit_upper_16bits,
u16);
372 _(bridge_control,
u16);
418 } __clib_packed pci_capability_regs_t;
423 pci_capability_regs_t *
c;
431 while (ttl-- && next_offset >= 0x40)
433 c = (
void *) t + (next_offset & ~3);
434 if ((
u8) c->type == 0xff)
436 if (c->type == cap_type)
438 next_offset = c->next_offset;
446 pci_capability_regs_t header;
448 #define PCI_PM_CAP_VER_MASK 0x0007 449 #define PCI_PM_CAP_PME_CLOCK 0x0008 450 #define PCI_PM_CAP_RESERVED 0x0010 451 #define PCI_PM_CAP_DSI 0x0020 452 #define PCI_PM_CAP_AUX_POWER 0x01C0 453 #define PCI_PM_CAP_D1 0x0200 454 #define PCI_PM_CAP_D2 0x0400 455 #define PCI_PM_CAP_PME 0x0800 456 #define PCI_PM_CAP_PME_MASK 0xF800 457 #define PCI_PM_CAP_PME_D0 0x0800 458 #define PCI_PM_CAP_PME_D1 0x1000 459 #define PCI_PM_CAP_PME_D2 0x2000 460 #define PCI_PM_CAP_PME_D3 0x4000 461 #define PCI_PM_CAP_PME_D3cold 0x8000 463 #define PCI_PM_CTRL_STATE_MASK 0x0003 464 #define PCI_PM_CTRL_PME_ENABLE 0x0100 465 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 466 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 467 #define PCI_PM_CTRL_PME_STATUS 0x8000 469 #define PCI_PM_PPB_B2_B3 0x40 470 #define PCI_PM_BPCC_ENABLE 0x80 472 } __clib_packed pci_power_management_regs_t;
477 pci_capability_regs_t header;
479 u8 rest_of_capability_flags;
483 #define PCI_AGP_RQ_MASK 0xff000000 484 #define PCI_AGP_SBA 0x0200 485 #define PCI_AGP_64BIT 0x0020 486 #define PCI_AGP_ALLOW_TRANSACTIONS 0x0100 487 #define PCI_AGP_FW 0x0010 488 #define PCI_AGP_RATE4 0x0004 489 #define PCI_AGP_RATE2 0x0002 490 #define PCI_AGP_RATE1 0x0001 491 } __clib_packed pci_agp_regs_t;
496 pci_capability_regs_t header;
498 #define PCI_VPD_ADDR_MASK 0x7fff 499 #define PCI_VPD_ADDR_F 0x8000 501 } __clib_packed pci_vpd_regs_t;
506 pci_capability_regs_t header;
508 #define PCI_SID_ESR_NSLOTS 0x1f 509 #define PCI_SID_ESR_FIC 0x20 511 } __clib_packed pci_sid_regs_t;
516 pci_capability_regs_t header;
518 #define PCI_MSI_FLAGS_ENABLE (1 << 0) 519 #define PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE(x) ((x >> 1) & 0x7) 520 #define PCI_MSI_FLAGS_MAX_QUEUE_SIZE(x) (((x) & 0x7) << 1) 521 #define PCI_MSI_FLAGS_GET_QUEUE_SIZE(x) ((x >> 4) & 0x7) 522 #define PCI_MSI_FLAGS_QUEUE_SIZE(x) (((x) & 0x7) << 4) 523 #define PCI_MSI_FLAGS_64BIT (1 << 7) 524 #define PCI_MSI_FLAGS_MASKBIT (1 << 8) 528 } __clib_packed pci_msi32_regs_t;
532 pci_capability_regs_t header;
537 } __clib_packed pci_msi64_regs_t;
542 pci_capability_regs_t header;
544 #define PCI_CHSWP_DHA 0x01 545 #define PCI_CHSWP_EIM 0x02 546 #define PCI_CHSWP_PIE 0x04 547 #define PCI_CHSWP_LOO 0x08 548 #define PCI_CHSWP_PI 0x30 549 #define PCI_CHSWP_EXT 0x40 550 #define PCI_CHSWP_INS 0x80 551 } __clib_packed pci_chswp_regs_t;
556 pci_capability_regs_t header;
558 #define PCIX_CMD_DPERR_E 0x0001 559 #define PCIX_CMD_ERO 0x0002 560 #define PCIX_CMD_MAX_READ 0x000c 561 #define PCIX_CMD_MAX_SPLIT 0x0070 562 #define PCIX_CMD_VERSION(x) (((x) >> 12) & 3) 564 #define PCIX_STATUS_DEVFN 0x000000ff 565 #define PCIX_STATUS_BUS 0x0000ff00 566 #define PCIX_STATUS_64BIT 0x00010000 567 #define PCIX_STATUS_133MHZ 0x00020000 568 #define PCIX_STATUS_SPL_DISC 0x00040000 569 #define PCIX_STATUS_UNX_SPL 0x00080000 570 #define PCIX_STATUS_COMPLEX 0x00100000 571 #define PCIX_STATUS_MAX_READ 0x00600000 572 #define PCIX_STATUS_MAX_SPLIT 0x03800000 573 #define PCIX_STATUS_MAX_CUM 0x1c000000 574 #define PCIX_STATUS_SPL_ERR 0x20000000 575 #define PCIX_STATUS_266MHZ 0x40000000 576 #define PCIX_STATUS_533MHZ 0x80000000 577 } __clib_packed pcix_config_regs_t;
590 int size = 1 << (code + 7);
598 pci_capability_regs_t header;
599 u16 pcie_capabilities;
600 #define PCIE_CAP_VERSION(x) (((x) >> 0) & 0xf) 601 #define PCIE_CAP_DEVICE_TYPE(x) (((x) >> 4) & 0xf) 602 #define PCIE_DEVICE_TYPE_ENDPOINT 0 603 #define PCIE_DEVICE_TYPE_LEGACY_ENDPOINT 1 604 #define PCIE_DEVICE_TYPE_ROOT_PORT 4 606 #define PCIE_DEVICE_TYPE_SWITCH_UPSTREAM 5 607 #define PCIE_DEVICE_TYPE_SWITCH_DOWNSTREAM 6 608 #define PCIE_DEVICE_TYPE_PCIE_TO_PCI_BRIDGE 7 609 #define PCIE_DEVICE_TYPE_PCI_TO_PCIE_BRIDGE 8 611 #define PCIE_DEVICE_TYPE_ROOT_COMPLEX_ENDPOINT 9 612 #define PCIE_DEVICE_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10 613 #define PCIE_CAP_SLOW_IMPLEMENTED (1 << 8) 614 #define PCIE_CAP_MSI_IRQ(x) (((x) >> 9) & 0x1f) 615 u32 dev_capabilities;
616 #define PCIE_DEVCAP_MAX_PAYLOAD(x) (128 << (((x) >> 0) & 0x7)) 617 #define PCIE_DEVCAP_PHANTOM_BITS(x) (((x) >> 3) & 0x3) 618 #define PCIE_DEVCAP_EXTENTED_TAG (1 << 5) 619 #define PCIE_DEVCAP_L0S 0x1c0 620 #define PCIE_DEVCAP_L1 0xe00 621 #define PCIE_DEVCAP_ATN_BUT 0x1000 622 #define PCIE_DEVCAP_ATN_IND 0x2000 623 #define PCIE_DEVCAP_PWR_IND 0x4000 624 #define PCIE_DEVCAP_PWR_VAL 0x3fc0000 625 #define PCIE_DEVCAP_PWR_SCL 0xc000000 627 #define PCIE_CTRL_CERE 0x0001 628 #define PCIE_CTRL_NFERE 0x0002 629 #define PCIE_CTRL_FERE 0x0004 630 #define PCIE_CTRL_URRE 0x0008 631 #define PCIE_CTRL_RELAX_EN 0x0010 632 #define PCIE_CTRL_MAX_PAYLOAD(n) (((n) & 7) << 5) 633 #define PCIE_CTRL_EXT_TAG 0x0100 634 #define PCIE_CTRL_PHANTOM 0x0200 635 #define PCIE_CTRL_AUX_PME 0x0400 636 #define PCIE_CTRL_NOSNOOP_EN 0x0800 637 #define PCIE_CTRL_MAX_READ_REQUEST(n) (((n) & 7) << 12) 639 #define PCIE_DEVSTA_AUXPD 0x10 640 #define PCIE_DEVSTA_TRPND 0x20 641 u32 link_capabilities;
644 u32 slot_capabilities;
648 #define PCIE_RTCTL_SECEE 0x01 649 #define PCIE_RTCTL_SENFEE 0x02 650 #define PCIE_RTCTL_SEFEE 0x04 651 #define PCIE_RTCTL_PMEIE 0x08 652 #define PCIE_RTCTL_CRSSVE 0x10 653 u16 root_capabilities;
655 u32 dev_capabilities2;
658 u32 link_capabilities2;
661 u32 slot_capabilities2;
664 } __clib_packed pcie_config_regs_t;
680 u16 next_capability:12;
681 } __clib_packed pcie_capability_regs_t;
685 pcie_capability_regs_t header;
686 u32 uncorrectable_status;
687 #define PCIE_ERROR_UNC_LINK_TRAINING (1 << 0) 688 #define PCIE_ERROR_UNC_DATA_LINK_PROTOCOL (1 << 4) 689 #define PCIE_ERROR_UNC_SURPRISE_DOWN (1 << 5) 690 #define PCIE_ERROR_UNC_POISONED_TLP (1 << 12) 691 #define PCIE_ERROR_UNC_FLOW_CONTROL (1 << 13) 692 #define PCIE_ERROR_UNC_COMPLETION_TIMEOUT (1 << 14) 693 #define PCIE_ERROR_UNC_COMPLETER_ABORT (1 << 15) 694 #define PCIE_ERROR_UNC_UNEXPECTED_COMPLETION (1 << 16) 695 #define PCIE_ERROR_UNC_RX_OVERFLOW (1 << 17) 696 #define PCIE_ERROR_UNC_MALFORMED_TLP (1 << 18) 697 #define PCIE_ERROR_UNC_CRC_ERROR (1 << 19) 698 #define PCIE_ERROR_UNC_UNSUPPORTED_REQUEST (1 << 20) 699 u32 uncorrectable_mask;
700 u32 uncorrectable_severity;
701 u32 correctable_status;
702 #define PCIE_ERROR_COR_RX_ERROR (1 << 0) 703 #define PCIE_ERROR_COR_BAD_TLP (1 << 6) 704 #define PCIE_ERROR_COR_BAD_DLLP (1 << 7) 705 #define PCIE_ERROR_COR_REPLAY_ROLLOVER (1 << 8) 706 #define PCIE_ERROR_COR_REPLAY_TIMER (1 << 12) 707 #define PCIE_ERROR_COR_ADVISORY (1 << 13) 708 u32 correctable_mask;
713 u16 correctable_error_source;
715 } __clib_packed pcie_advanced_error_regs_t;
718 #define PCI_VC_PORT_REG1 4 719 #define PCI_VC_PORT_REG2 8 720 #define PCI_VC_PORT_CTRL 12 721 #define PCI_VC_PORT_STATUS 14 722 #define PCI_VC_RES_CAP 16 723 #define PCI_VC_RES_CTRL 20 724 #define PCI_VC_RES_STATUS 26 727 #define PCI_PWR_DSR 4 728 #define PCI_PWR_DATA 8 729 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 730 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 731 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 732 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 733 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 734 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 735 #define PCI_PWR_CAP 12 736 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) static pci_device_class_t pci_device_class_base(pci_device_class_t c)
pci_config_header_t header
u8 capability_list_offset
static void * pci_config_find_capability(pci_config_type0_regs_t *t, int cap_type)
enum pcie_capability_type pcie_capability_type_t
enum pci_capability_type pci_capability_type_t
static void pci_config_header_little_to_host(pci_config_header_t *r)
static uword min_log2(uword x)
u16 prefetchable_memory_limit
static void pci_config_type1_little_to_host(pci_config_type1_regs_t *r)
u16 io_limit_upper_16bits
u8 first_capability_offset
static int pcie_size_to_code(int bytes)
vl_api_fib_path_type_t type
u8 secondary_bus_latency_timer
static void pci_config_type0_little_to_host(pci_config_type0_regs_t *r)
#define PCI_STATUS_CAPABILITY_LIST
manual_print typedef address
static uword is_pow2(uword x)
#define CLIB_ARCH_IS_BIG_ENDIAN
u32 prefetchable_memory_limit_upper_32bits
static int pcie_code_to_size(int code)
u32 prefetchable_memory_base_upper_32bits
pci_config_header_t header