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FD.io VPP
v20.05.1-6-gf53edbc3b
Vector Packet Processing
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FD.io VPP
v20.05.1-6-gf53edbc3b
Vector Packet Processing
|
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Data Structures | |
| struct | vmxnet3_rx_ring |
| struct | vmxnet3_rx_comp_ring |
| struct | vmxnet3_rxq_t |
| struct | vmxnet3_tx_ring |
| struct | vmxnet3_tx_comp_ring |
| struct | vmxnet3_txq_t |
| struct | vmxnet3_device_t |
| struct | vmxnet3_main_t |
| struct | vmxnet3_create_if_args_t |
| struct | vmxnet3_input_trace_t |
Macros | |
| #define | foreach_vmxnet3_tx_func_error |
| #define | foreach_vmxnet3_rxmode_flags |
| #define | foreach_vmxnet3_show_entry |
| #define | foreach_vmxnet3_feature_flags |
| #define | foreach_vmxnet3_rss_hash_type |
| #define | VMXNET3_RSS_HASH_FUNC_TOEPLITZ 1 |
| #define | VMXNET3_RSS_MAX_KEY_SZ 40 |
| #define | VMXNET3_RSS_MAX_IND_TABLE_SZ 128 |
| #define | VMXNET3_TXQ_MAX 8 |
| #define | VMXNET3_RXQ_MAX 16 |
| #define | VMXNET3_TX_START(vd) ((vd)->queues) |
| #define | VMXNET3_RX_START(vd) ((vd)->queues + (vd)->num_tx_queues * sizeof (vmxnet3_tx_queue)) |
| #define | VMXNET3_REG_IMR 0x0000 /* Interrupt Mask Register */ |
| #define | VMXNET3_REG_TXPROD 0x0600 /* Tx Producer Index */ |
| #define | VMXNET3_REG_RXPROD 0x0800 /* Rx Producer Index for ring 1 */ |
| #define | VMXNET3_REG_RXPROD2 0x0A00 /* Rx Producer Index for ring 2 */ |
| #define | VMXNET3_REG_VRRS 0x0000 /* VMXNET3 Revision Report Selection */ |
| #define | VMXNET3_REG_UVRS 0x0008 /* UPT Version Report Selection */ |
| #define | VMXNET3_REG_DSAL 0x0010 /* Driver Shared Address Low */ |
| #define | VMXNET3_REG_DSAH 0x0018 /* Driver Shared Address High */ |
| #define | VMXNET3_REG_CMD 0x0020 /* Command */ |
| #define | VMXNET3_REG_MACL 0x0028 /* MAC Address Low */ |
| #define | VMXNET3_REG_MACH 0x0030 /* MAC Address High */ |
| #define | VMXNET3_REG_ICR 0x0038 /* Interrupt Cause Register */ |
| #define | VMXNET3_REG_ECR 0x0040 /* Event Cause Register */ |
| #define | VMXNET3_VLAN_LEN 4 |
| #define | VMXNET3_FCS_LEN 4 |
| #define | VMXNET3_MTU (1514 + VMXNET3_VLAN_LEN + VMXNET3_FCS_LEN) |
| #define | VMXNET3_RXF_BTYPE (1 << 14) /* rx body buffer type */ |
| #define | VMXNET3_RXF_GEN (1 << 31) /* rx generation */ |
| #define | VMXNET3_RXCF_CKSUM_MASK (0xFFFF) /* rx checksum mask */ |
| #define | VMXNET3_RXCF_TUC (1 << 16) /* rx udp/tcp checksum correct */ |
| #define | VMXNET3_RXCF_UDP (1 << 17) /* rx udp packet */ |
| #define | VMXNET3_RXCF_TCP (1 << 18) /* rx tcp packet */ |
| #define | VMXNET3_RXCF_IPC (1 << 19) /* rx ip checksum correct */ |
| #define | VMXNET3_RXCF_IP6 (1 << 20) /* rx ip6 packet */ |
| #define | VMXNET3_RXCF_IP4 (1 << 21) /* rx ip4 packet */ |
| #define | VMXNET3_RXCF_CT (0x7F << 24) /* rx completion type 24-30, 7 bits */ |
| #define | VMXNET3_RXCF_GEN (1 << 31) /* rx completion generation */ |
| #define | VMXNET3_RXC_INDEX (0xFFF) /* rx completion index mask */ |
| #define | foreach_vmxnet3_offload |
| #define | VMXNET3_TXF_GEN (1 << 14) /* tx generation */ |
| #define | VMXNET3_TXF_OM(x) ((x) << 10) /* tx offload mode */ |
| #define | VMXNET3_TXF_MSSCOF(x) ((x) << 18) /* tx MSS checksum offset, flags */ |
| #define | VMXNET3_TXF_EOP (1 << 12) /* tx end of packet */ |
| #define | VMXNET3_TXF_CQ (1 << 13) /* tx completion request */ |
| #define | VMXNET3_TXCF_GEN (1 << 31) /* tx completion generation */ |
| #define | VMXNET3_TXC_INDEX (0xFFF) /* tx completion index mask */ |
| #define | VMXNET3_RX_RING_SIZE 2 |
| #define | VMXNET3_INPUT_REFILL_THRESHOLD 32 |
| #define | VMXNET3_NUM_TX_DESC 1024 |
| #define | VMXNET3_NUM_TX_COMP VMXNET3_NUM_TX_DESC |
| #define | VMXNET3_NUM_RX_DESC 1024 |
| #define | VMXNET3_NUM_RX_COMP VMXNET3_NUM_RX_DESC |
| #define | VMXNET3_VERSION_MAGIC 0x69505845 |
| #define | VMXNET3_SHARED_MAGIC 0xbabefee1 |
| #define | VMXNET3_VERSION_SELECT 1 |
| #define | VMXNET3_UPT_VERSION_SELECT 1 |
| #define | VMXNET3_MAX_INTRS 25 |
| #define | VMXNET3_IC_DISABLE_ALL 0x1 |
| #define | VMXNET3_GOS_BITS_32 (1 << 0) |
| #define | VMXNET3_GOS_BITS_64 (2 << 0) |
| #define | VMXNET3_GOS_TYPE_LINUX (1 << 2) |
| #define | VMXNET3_RXCL_LEN_MASK (0x3FFF) |
| #define | VMXNET3_RXCL_ERROR (1 << 14) |
| #define | VMXNET3_RXCI_EOP (1 << 14) /* end of packet */ |
| #define | VMXNET3_RXCI_SOP (1 << 15) /* start of packet */ |
| #define | VMXNET3_RXCI_CNC (1 << 30) /* Checksum not calculated */ |
| #define | VMXNET3_RXCOMP_TYPE (3 << 24) /* RX completion descriptor */ |
| #define | VMXNET3_RXCOMP_TYPE_LRO (4 << 24) /* RX completion descriptor for LRO */ |
| #define | VMXNET3_RXECF_MSS_MASK (0xFFFF) |
| #define | foreach_vmxnet3_device_flags |
| #define | foreach_vmxnet3_set_cmds |
| #define | foreach_vmxnet3_get_cmds |
| #define | vmxnet3_log_debug(dev, f, ...) |
| #define | vmxnet3_log_error(dev, f, ...) |
Enumerations | |
| enum | vmxnet3_tx_func_error_t { VMXNET3_TX_N_ERROR } |
| enum | { foreach_vmxnet3_rxmode_flags } |
| enum | { foreach_vmxnet3_show_entry } |
| enum | { foreach_vmxnet3_feature_flags } |
| enum | { foreach_vmxnet3_rss_hash_type } |
| enum | { foreach_vmxnet3_offload } |
| enum | { foreach_vmxnet3_device_flags } |
| enum | { foreach_vmxnet3_set_cmds } |
| enum | { foreach_vmxnet3_get_cmds } |
Functions | |
| typedef | CLIB_PACKED (struct { u32 version;u32 guest_info;u32 version_support;u32 upt_version_support;u64 upt_features;u64 driver_data_address;u64 queue_desc_address;u32 driver_data_len;u32 queue_desc_len;u32 mtu;u16 max_num_rx_sg;u8 num_tx_queues;u8 num_rx_queues;u32 pad[4];}) vmxnet3_misc_config |
| typedef | CLIB_PACKED (struct { u8 mask_mode;u8 num_intrs;u8 event_intr_index;u8 moderation_level[VMXNET3_MAX_INTRS];u32 control;u32 pad[2];}) vmxnet3_interrupt_config |
| typedef | CLIB_PACKED (struct { u32 mode;u16 multicast_len;u16 pad;u64 multicast_address;u8 vlan_filter[512];}) vmxnet3_rx_filter_config |
| typedef | CLIB_PACKED (struct { u32 version;u32 length;u64 address;}) vmxnet3_variable_config |
| typedef | CLIB_PACKED (struct { u32 magic;u32 pad;vmxnet3_misc_config misc;vmxnet3_interrupt_config interrupt;vmxnet3_rx_filter_config rx_filter;vmxnet3_variable_config rss;vmxnet3_variable_config pattern;vmxnet3_variable_config plugin;u32 ecr;u32 pad1[5];}) vmxnet3_shared |
| typedef | CLIB_PACKED (struct { u8 stopped;u8 pad[3];u32 error;}) vmxnet3_queue_status |
| typedef | CLIB_PACKED (struct { u32 num_deferred;u32 threshold;u64 pad;}) vmxnet3_tx_queue_control |
| typedef | CLIB_PACKED (struct { u64 desc_address;u64 data_address;u64 comp_address;u64 driver_data_address;u64 pad;u32 num_desc;u32 num_data;u32 num_comp;u32 driver_data_len;u8 intr_index;u8 pad1;u16 data_address_size;u8 pad2[4];}) vmxnet3_tx_queue_config |
| typedef | CLIB_PACKED (struct { u64 tso_pkts;u64 tso_bytes;u64 ucast_pkts;u64 ucast_bytes;u64 mcast_pkts;u64 mcast_bytes;u64 bcast_pkts;u64 bcast_bytes;u64 error_pkts;u64 discard_pkts;}) vmxnet3_tx_stats |
| typedef | CLIB_PACKED (struct { vmxnet3_tx_queue_control ctrl;vmxnet3_tx_queue_config cfg;vmxnet3_queue_status status;vmxnet3_tx_stats stats;u8 pad[88];}) vmxnet3_tx_queue |
| typedef | CLIB_PACKED (struct { u8 update_prod;u8 pad[7];u64 pad1;}) vmxnet3_rx_queue_control |
| typedef | CLIB_PACKED (struct { u64 desc_address[2];u64 comp_address;u64 driver_data_address;u64 data_address;u32 num_desc[2];u32 num_comp;u32 driver_data_len;u8 intr_index;u8 pad1;u16 data_address_size;u8 pad2[4];}) vmxnet3_rx_queue_config |
| typedef | CLIB_PACKED (struct { u64 lro_pkts;u64 lro_bytes;u64 ucast_pkts;u64 ucast_bytes;u64 mcast_pkts;u64 mcast_bytes;u64 bcast_pkts;u64 bcast_bytes;u64 nobuf_pkts;u64 error_pkts;}) vmxnet3_rx_stats |
| typedef | CLIB_PACKED (struct { vmxnet3_rx_queue_control ctrl;vmxnet3_rx_queue_config cfg;vmxnet3_queue_status status;vmxnet3_rx_stats stats;u8 pad[88];}) vmxnet3_rx_queue |
| typedef | CLIB_PACKED (struct { u64 address;u32 flags;u32 pad;}) vmxnet3_rx_desc |
| typedef | CLIB_PACKED (struct { u32 index;u32 rss;u32 len;u32 flags;}) vmxnet3_rx_comp |
| typedef | CLIB_PACKED (struct { u32 dword1;u8 seg_cnt;u8 dup_ack_cnt;u16 ts_delta;u32 dword2;u32 flags;}) vmxnet3_rx_comp_ext |
| typedef | CLIB_PACKED (struct { u32 index;u32 pad[2];u32 flags;}) vmxnet3_tx_comp |
| typedef | CLIB_PACKED (struct { u64 address;u32 flags[2];}) vmxnet3_tx_desc |
| typedef | CLIB_PACKED (struct { u16 hash_type;u16 hash_func;u16 hash_key_sz;u16 ind_table_sz;u8 hash_key[VMXNET3_RSS_MAX_KEY_SZ];u8 ind_table[VMXNET3_RSS_MAX_IND_TABLE_SZ];}) vmxnet3_rss_shared |
| void | vmxnet3_create_if (vlib_main_t *vm, vmxnet3_create_if_args_t *args) |
| void | vmxnet3_delete_if (vlib_main_t *vm, vmxnet3_device_t *ad) |
| clib_error_t * | vmxnet3_plugin_api_hookup (vlib_main_t *vm) |
| static_always_inline void | vmxnet3_reg_write_inline (vmxnet3_device_t *vd, u8 bar, u32 addr, u32 val) |
| static_always_inline void | vmxnet3_reg_write (vmxnet3_device_t *vd, u8 bar, u32 addr, u32 val) |
| static_always_inline u32 | vmxnet3_reg_read (vmxnet3_device_t *vd, u8 bar, u32 addr) |
| static_always_inline uword | vmxnet3_dma_addr (vlib_main_t *vm, vmxnet3_device_t *vd, void *p) |
| static_always_inline void | vmxnet3_rx_ring_advance_produce (vmxnet3_rxq_t *rxq, vmxnet3_rx_ring *ring) |
| static_always_inline clib_error_t * | vmxnet3_rxq_refill_ring0 (vlib_main_t *vm, vmxnet3_device_t *vd, vmxnet3_rxq_t *rxq) |
| static_always_inline clib_error_t * | vmxnet3_rxq_refill_ring1 (vlib_main_t *vm, vmxnet3_device_t *vd, vmxnet3_rxq_t *rxq) |
Variables | |
| vmxnet3_main_t | vmxnet3_main |
| vlib_node_registration_t | vmxnet3_input_node |
| (constructor) VLIB_REGISTER_NODE (vmxnet3_input_node) More... | |
| vnet_device_class_t | vmxnet3_device_class |
| format_function_t | format_vmxnet3_device |
| format_function_t | format_vmxnet3_device_name |
| format_function_t | format_vmxnet3_input_trace |
| #define foreach_vmxnet3_device_flags |
| #define foreach_vmxnet3_feature_flags |
| #define foreach_vmxnet3_get_cmds |
| #define foreach_vmxnet3_offload |
| #define foreach_vmxnet3_rss_hash_type |
| #define foreach_vmxnet3_rxmode_flags |
| #define foreach_vmxnet3_set_cmds |
| #define foreach_vmxnet3_show_entry |
| #define foreach_vmxnet3_tx_func_error |
| #define vmxnet3_log_debug | ( | dev, | |
| f, | |||
| ... | |||
| ) |
| #define vmxnet3_log_error | ( | dev, | |
| f, | |||
| ... | |||
| ) |
| #define VMXNET3_MTU (1514 + VMXNET3_VLAN_LEN + VMXNET3_FCS_LEN) |
| #define VMXNET3_NUM_RX_COMP VMXNET3_NUM_RX_DESC |
| #define VMXNET3_NUM_TX_COMP VMXNET3_NUM_TX_DESC |
| #define VMXNET3_REG_DSAH 0x0018 /* Driver Shared Address High */ |
| #define VMXNET3_REG_DSAL 0x0010 /* Driver Shared Address Low */ |
| #define VMXNET3_REG_ICR 0x0038 /* Interrupt Cause Register */ |
| #define VMXNET3_REG_IMR 0x0000 /* Interrupt Mask Register */ |
| #define VMXNET3_REG_RXPROD 0x0800 /* Rx Producer Index for ring 1 */ |
| #define VMXNET3_REG_RXPROD2 0x0A00 /* Rx Producer Index for ring 2 */ |
| #define VMXNET3_REG_UVRS 0x0008 /* UPT Version Report Selection */ |
| #define VMXNET3_REG_VRRS 0x0000 /* VMXNET3 Revision Report Selection */ |
| #define VMXNET3_RX_START | ( | vd | ) | ((vd)->queues + (vd)->num_tx_queues * sizeof (vmxnet3_tx_queue)) |
| #define VMXNET3_RXC_INDEX (0xFFF) /* rx completion index mask */ |
| #define VMXNET3_RXCF_CKSUM_MASK (0xFFFF) /* rx checksum mask */ |
| #define VMXNET3_RXCF_CT (0x7F << 24) /* rx completion type 24-30, 7 bits */ |
| #define VMXNET3_RXCF_GEN (1 << 31) /* rx completion generation */ |
| #define VMXNET3_RXCF_IPC (1 << 19) /* rx ip checksum correct */ |
| #define VMXNET3_RXCF_TUC (1 << 16) /* rx udp/tcp checksum correct */ |
| #define VMXNET3_RXCI_CNC (1 << 30) /* Checksum not calculated */ |
| #define VMXNET3_RXCOMP_TYPE (3 << 24) /* RX completion descriptor */ |
| #define VMXNET3_RXCOMP_TYPE_LRO (4 << 24) /* RX completion descriptor for LRO */ |
| #define VMXNET3_RXF_BTYPE (1 << 14) /* rx body buffer type */ |
| #define VMXNET3_TXC_INDEX (0xFFF) /* tx completion index mask */ |
| #define VMXNET3_TXCF_GEN (1 << 31) /* tx completion generation */ |
| #define VMXNET3_TXF_CQ (1 << 13) /* tx completion request */ |
| #define VMXNET3_TXF_OM | ( | x | ) | ((x) << 10) /* tx offload mode */ |
| typedef CLIB_PACKED | ( | struct { u32 version;u32 guest_info;u32 version_support;u32 upt_version_support;u64 upt_features;u64 driver_data_address;u64 queue_desc_address;u32 driver_data_len;u32 queue_desc_len;u32 mtu;u16 max_num_rx_sg;u8 num_tx_queues;u8 num_rx_queues;u32 pad[4];} | ) |
| typedef CLIB_PACKED | ( | struct { u8 mask_mode;u8 num_intrs;u8 event_intr_index;u8 moderation_level[VMXNET3_MAX_INTRS];u32 control;u32 pad[2];} | ) |
| typedef CLIB_PACKED | ( | struct { u32 mode;u16 multicast_len;u16 pad;u64 multicast_address;u8 vlan_filter[512];} | ) |
| typedef CLIB_PACKED | ( | struct { u32 magic;u32 pad;vmxnet3_misc_config misc;vmxnet3_interrupt_config interrupt;vmxnet3_rx_filter_config rx_filter;vmxnet3_variable_config rss;vmxnet3_variable_config pattern;vmxnet3_variable_config plugin;u32 ecr;u32 pad1[5];} | ) |
| typedef CLIB_PACKED | ( | struct { u64 desc_address;u64 data_address;u64 comp_address;u64 driver_data_address;u64 pad;u32 num_desc;u32 num_data;u32 num_comp;u32 driver_data_len;u8 intr_index;u8 pad1;u16 data_address_size;u8 pad2[4];} | ) |
| typedef CLIB_PACKED | ( | struct { u64 tso_pkts;u64 tso_bytes;u64 ucast_pkts;u64 ucast_bytes;u64 mcast_pkts;u64 mcast_bytes;u64 bcast_pkts;u64 bcast_bytes;u64 error_pkts;u64 discard_pkts;} | ) |
| typedef CLIB_PACKED | ( | struct { vmxnet3_tx_queue_control ctrl;vmxnet3_tx_queue_config cfg;vmxnet3_queue_status status;vmxnet3_tx_stats stats;u8 pad[88];} | ) |
| typedef CLIB_PACKED | ( | struct { u64 desc_address[2];u64 comp_address;u64 driver_data_address;u64 data_address;u32 num_desc[2];u32 num_comp;u32 driver_data_len;u8 intr_index;u8 pad1;u16 data_address_size;u8 pad2[4];} | ) |
| typedef CLIB_PACKED | ( | struct { u64 lro_pkts;u64 lro_bytes;u64 ucast_pkts;u64 ucast_bytes;u64 mcast_pkts;u64 mcast_bytes;u64 bcast_pkts;u64 bcast_bytes;u64 nobuf_pkts;u64 error_pkts;} | ) |
| typedef CLIB_PACKED | ( | struct { vmxnet3_rx_queue_control ctrl;vmxnet3_rx_queue_config cfg;vmxnet3_queue_status status;vmxnet3_rx_stats stats;u8 pad[88];} | ) |
| typedef CLIB_PACKED | ( | struct { u32 dword1;u8 seg_cnt;u8 dup_ack_cnt;u16 ts_delta;u32 dword2;u32 flags;} | ) |
| typedef CLIB_PACKED | ( | struct { u16 hash_type;u16 hash_func;u16 hash_key_sz;u16 ind_table_sz;u8 hash_key[VMXNET3_RSS_MAX_KEY_SZ];u8 ind_table[VMXNET3_RSS_MAX_IND_TABLE_SZ];} | ) |
| void vmxnet3_create_if | ( | vlib_main_t * | vm, |
| vmxnet3_create_if_args_t * | args | ||
| ) |
| void vmxnet3_delete_if | ( | vlib_main_t * | vm, |
| vmxnet3_device_t * | ad | ||
| ) |
| static_always_inline uword vmxnet3_dma_addr | ( | vlib_main_t * | vm, |
| vmxnet3_device_t * | vd, | ||
| void * | p | ||
| ) |
| clib_error_t* vmxnet3_plugin_api_hookup | ( | vlib_main_t * | vm | ) |
Definition at line 193 of file vmxnet3_api.c.
Here is the call graph for this function: Here is the caller graph for this function:| static_always_inline u32 vmxnet3_reg_read | ( | vmxnet3_device_t * | vd, |
| u8 | bar, | ||
| u32 | addr | ||
| ) |
| static_always_inline void vmxnet3_reg_write | ( | vmxnet3_device_t * | vd, |
| u8 | bar, | ||
| u32 | addr, | ||
| u32 | val | ||
| ) |
| static_always_inline void vmxnet3_reg_write_inline | ( | vmxnet3_device_t * | vd, |
| u8 | bar, | ||
| u32 | addr, | ||
| u32 | val | ||
| ) |
| static_always_inline void vmxnet3_rx_ring_advance_produce | ( | vmxnet3_rxq_t * | rxq, |
| vmxnet3_rx_ring * | ring | ||
| ) |
| static_always_inline clib_error_t* vmxnet3_rxq_refill_ring0 | ( | vlib_main_t * | vm, |
| vmxnet3_device_t * | vd, | ||
| vmxnet3_rxq_t * | rxq | ||
| ) |
| static_always_inline clib_error_t* vmxnet3_rxq_refill_ring1 | ( | vlib_main_t * | vm, |
| vmxnet3_device_t * | vd, | ||
| vmxnet3_rxq_t * | rxq | ||
| ) |
| format_function_t format_vmxnet3_device |
| format_function_t format_vmxnet3_device_name |
| format_function_t format_vmxnet3_input_trace |
| vnet_device_class_t vmxnet3_device_class |
| vlib_node_registration_t vmxnet3_input_node |
| vmxnet3_main_t vmxnet3_main |
1.8.13