23 #if __x86_64__ || __i386__ || __aarch64__ 26 #ifndef CLIB_HAVE_VEC128 27 #warning HACK: ixge driver wont really work, missing u32x4 28 typedef unsigned long long u32x4;
38 #include <vpp/app/version.h> 40 #define IXGE_ALWAYS_POLL 0 42 #define EVENT_SET_FLAGS 0 43 #define IXGE_HWBP_RACE_ELOG 0 45 #define PCI_VENDOR_ID_INTEL 0x8086 48 #define XGE_PHY_DEV_TYPE_PMA_PMD 1 49 #define XGE_PHY_DEV_TYPE_PHY_XS 4 50 #define XGE_PHY_ID1 0x2 51 #define XGE_PHY_ID2 0x3 52 #define XGE_PHY_CONTROL 0x0 53 #define XGE_PHY_CONTROL_RESET (1 << 15) 94 u32 fw_mask = sw_mask << 5;
101 done = (m & fw_mask) == 0;
124 const u32 busy_bit = 1 << 30;
130 ASSERT (reg_index < (1 << 16));
131 ASSERT (dev_type < (1 << 5));
137 reg_index | (dev_type << 16) | (xd->
178 v |= (sda != 0) << 3;
179 v |= (scl != 0) << 1;
191 *sda = (v & (1 << 2)) != 0;
192 *scl = (v & (1 << 0)) != 0;
210 u32 tx_disable_bit = 1 << 3;
220 u32 is_10g_bit = 1 << 5;
230 u16 a,
id, reg_values_addr = 0;
233 if (a == 0 || a == 0xffff)
334 while (!(dr->
control & (1 << 25)))
385 case IXGE_82599_sfp_em:
386 case IXGE_82599_sfp_fcoe:
399 for (i = 0; i < 32; i++)
403 if (v != 0xffff && v != 0)
419 .function = (
char *) __FUNCTION__,.
format =
420 "ixge %d, phy id 0x%d mdio address %d",.format_args =
"i4i4i4",};
450 u32 is_ip4,
is_ip6, is_ip, is_tcp, is_udp;
453 s =
format (s,
"%s-owned",
457 format (s,
", length this descriptor %d, l3 offset %d",
461 s =
format (s,
", end-of-packet");
466 s =
format (s,
"layer2 error");
470 s =
format (s,
"layer 2 type %d", (s0 & 0x1f));
484 s =
format (s,
" checksum %s",
493 if ((is_ip = (is_ip4 | is_ip6)))
504 s =
format (s,
", tcp checksum %s",
508 s =
format (s,
", udp checksum %s",
523 s =
format (s,
"buffer 0x%Lx, %d packet bytes, %d bytes this buffer",
528 if ((v = (s0 >> 0) & 3))
529 s =
format (s,
"reserved 0x%x, ", v);
531 if ((v = (s0 >> 2) & 3))
532 s =
format (s,
"mac 0x%x, ", v);
534 if ((v = (s0 >> 4) & 0xf) != 3)
535 s =
format (s,
"type 0x%x, ", v);
537 s =
format (s,
"%s%s%s%s%s%s%s%s",
538 (s0 & (1 << 8)) ?
"eop, " :
"",
539 (s0 & (1 << 9)) ?
"insert-fcs, " :
"",
540 (s0 & (1 << 10)) ?
"reserved26, " :
"",
541 (s0 & (1 << 11)) ?
"report-status, " :
"",
542 (s0 & (1 << 12)) ?
"reserved28, " :
"",
543 (s0 & (1 << 13)) ?
"is-advanced, " :
"",
544 (s0 & (1 << 14)) ?
"vlan-enable, " :
"",
545 (s0 & (1 << 15)) ?
"tx-segmentation, " :
"");
547 if ((v = s1 & 0xf) != 0)
548 s =
format (s,
"status 0x%x, ", v);
550 if ((v = (s1 >> 4) & 0xf))
551 s =
format (s,
"context 0x%x, ", v);
553 if ((v = (s1 >> 8) & 0x3f))
554 s =
format (s,
"options 0x%x, ", v);
595 s =
format (s,
"\n%Ubefore: %U",
598 s =
format (s,
"\n%Uafter : head/tail address 0x%Lx/0x%Lx",
602 s =
format (s,
"\n%Ubuffer 0x%x: %U",
616 #define foreach_ixge_error \ 617 _ (none, "no error") \ 618 _ (tx_full_drops, "tx ring full drops") \ 619 _ (ip4_checksum_error, "ip4 checksum errors") \ 620 _ (rx_alloc_fail, "rx buf alloc from free list failed") \ 621 _ (rx_alloc_no_physmem, "rx buf alloc failed no physmem") 625 #define _(f,s) IXGE_ERROR_##f, 634 u8 * next0,
u8 * error0,
u32 * flags0)
636 u8 is0_ip4, is0_ip6, n0, e0;
639 e0 = IXGE_ERROR_none;
646 ? IXGE_ERROR_ip4_checksum_error : e0);
659 ? VNET_BUFFER_F_L4_CHECKSUM_COMPUTED : 0);
663 ? 0 : VNET_BUFFER_F_L4_CHECKSUM_CORRECT);
674 u8 * next0,
u8 * error0,
u32 * flags0,
675 u8 * next1,
u8 * error1,
u32 * flags1)
677 u8 is0_ip4, is0_ip6, n0, e0;
678 u8 is1_ip4, is1_ip6, n1, e1;
681 e0 = e1 = IXGE_ERROR_none;
691 ? IXGE_ERROR_ip4_checksum_error : e0);
693 ? IXGE_ERROR_ip4_checksum_error : e1);
718 ? VNET_BUFFER_F_L4_CHECKSUM_COMPUTED : 0);
721 ? VNET_BUFFER_F_L4_CHECKSUM_COMPUTED : 0);
725 ? 0 : VNET_BUFFER_F_L4_CHECKSUM_CORRECT);
728 ? 0 : VNET_BUFFER_F_L4_CHECKSUM_CORRECT);
739 u32 * before_buffers,
746 u32 *b, n_left, is_sop, next_index_sop;
748 n_left = n_descriptors;
752 is_sop = dq->
rx.is_start_of_packet;
753 next_index_sop = dq->
rx.saved_start_of_packet_next_index;
757 u32 bi0, bi1, flags0, flags1;
760 u8 next0, error0, next1, error1;
770 bd[0].status[0], bd[0].status[2],
771 bd[1].status[0], bd[1].status[2],
772 &next0, &error0, &flags0,
773 &next1, &error1, &flags1);
775 next_index_sop = is_sop ? next0 : next_index_sop;
779 is_sop = (b0->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
781 next_index_sop = is_sop ? next1 : next_index_sop;
785 is_sop = (b1->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
822 bd[0].status[0], bd[0].status[2],
823 &next0, &error0, &flags0);
825 next_index_sop = is_sop ? next0 : next_index_sop;
829 is_sop = (b0->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
882 s =
format (s,
"\n%Udescriptor: %U",
886 s =
format (s,
"\n%Ubuffer 0x%x: %U",
922 u32 *b, n_left, is_sop;
924 n_left = n_descriptors;
944 is_sop = (b0->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
948 is_sop = (b1->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
982 is_sop = (b0->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1001 ASSERT (i0 < q->n_descriptors);
1002 ASSERT (i1 < q->n_descriptors);
1010 ASSERT (i0 < q->n_descriptors);
1011 ASSERT (i1 < q->n_descriptors);
1039 u32 start_descriptor_index,
1044 u32 n_left = n_descriptors;
1051 u32 descriptor_prefetch_rotor = 0;
1053 ASSERT (start_descriptor_index + n_descriptors <= dq->n_descriptors);
1062 u8 is_eop0, is_eop1;
1068 if ((descriptor_prefetch_rotor & 0x3) == 0)
1071 descriptor_prefetch_rotor += 2;
1076 to_free[0] = fi0 = to_tx[0];
1078 to_free += fi0 != 0;
1080 to_free[0] = fi1 = to_tx[1];
1082 to_free += fi1 != 0;
1091 is_eop0 = (b0->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1092 is_eop1 = (b1->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1107 template_status | (is_eop0 <<
1110 template_status | (is_eop1 <<
1113 len_sop = (is_sop ? 0 : len_sop) + len0;
1117 d_sop = is_eop0 ? d : d_sop;
1121 len_sop = (is_sop ? 0 : len_sop) + len1;
1125 d_sop = is_eop1 ? d : d_sop;
1138 to_free[0] = fi0 = to_tx[0];
1140 to_free += fi0 != 0;
1148 is_eop0 = (b0->
flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1158 template_status | (is_eop0 <<
1161 len_sop = (is_sop ? 0 : len_sop) + len0;
1165 d_sop = is_eop0 ? d : d_sop;
1174 start_descriptor_index);
1187 ASSERT (d_sop - d_start <= dq->n_descriptors);
1188 d_sop = d_sop - d_start == dq->
n_descriptors ? d_start : d_sop;
1195 return n_descriptors;
1206 u32 *from, n_left_tx, n_descriptors_to_tx, n_tail_drop;
1207 u32 queue_index = 0;
1231 i32 i, n_ok, i_eop, i_sop;
1234 for (i = n_left_tx - 1; i >= 0; i--)
1237 if (!(b->
flags & VLIB_BUFFER_NEXT_PRESENT))
1239 if (i_sop != ~0 && i_eop != ~0)
1253 .function = (
char *) __FUNCTION__,.
format =
1254 "ixge %d, ring full to tx %d head %d tail %d",.format_args =
1261 ed->instance = xd->device_index;
1262 ed->to_tx = n_descriptors_to_tx;
1267 if (n_ok < n_descriptors_to_tx)
1269 n_tail_drop = n_descriptors_to_tx - n_ok;
1272 IXGE_ERROR_tx_full_drops, n_tail_drop);
1275 n_descriptors_to_tx = n_ok;
1278 dq->
tx.n_buffers_on_ring += n_descriptors_to_tx;
1287 n_descriptors_to_tx -= n;
1294 if (n_descriptors_to_tx > 0)
1297 ixge_tx_no_wrap (xm, xd, dq, from, 0, n_descriptors_to_tx, &tx_state);
1299 ASSERT (n == n_descriptors_to_tx);
1332 ASSERT (dq->
tx.n_buffers_on_ring >= n);
1333 dq->
tx.n_buffers_on_ring -= (n - n_tail_drop);
1344 u32 start_descriptor_index,
u32 n_descriptors)
1350 static u32 *d_trace_buffers;
1351 u32 n_descriptors_left = n_descriptors;
1355 u32 bi_sop = dq->
rx.saved_start_of_packet_buffer_index;
1356 u32 bi_last = dq->
rx.saved_last_buffer_index;
1357 u32 next_index_sop = dq->
rx.saved_start_of_packet_next_index;
1358 u32 is_sop = dq->
rx.is_start_of_packet;
1359 u32 next_index, n_left_to_next, *to_next;
1365 ASSERT (start_descriptor_index + n_descriptors <= dq->n_descriptors);
1368 b_last = bi_last != ~0 ?
vlib_get_buffer (vm, bi_last) : &b_placeholder;
1369 next_index = dq->
rx.next_index;
1376 _vec_len (d_trace_save) = 0;
1377 _vec_len (d_trace_buffers) = 0;
1380 vec_add (d_trace_buffers, to_rx, n);
1386 if (l < n_descriptors_left)
1401 if (n_allocated == 0)
1403 IXGE_ERROR_rx_alloc_no_physmem, 1);
1406 IXGE_ERROR_rx_alloc_fail, 1);
1408 n_descriptors_left = l + n_allocated;
1410 n_descriptors = n_descriptors_left;
1417 while (n_descriptors_left > 0)
1421 while (n_descriptors_left >= 4 && n_left_to_next >= 2)
1425 u32 bi0, fi0, len0, l3_offset0, s20, s00, flags0;
1426 u32 bi1, fi1, len1, l3_offset1, s21, s01, flags1;
1427 u8 is_eop0, error0, next0;
1428 u8 is_eop1, error1, next1;
1447 goto found_hw_owned_descriptor_x2;
1486 &next0, &error0, &flags0,
1487 &next1, &error1, &flags1);
1489 next0 = is_sop ? next0 : next_index_sop;
1490 next1 = is_eop0 ? next1 : next0;
1491 next_index_sop = next1;
1493 b0->
flags |= flags0 | (!is_eop0 << VLIB_BUFFER_LOG2_NEXT_PRESENT);
1494 b1->
flags |= flags1 | (!is_eop1 << VLIB_BUFFER_LOG2_NEXT_PRESENT);
1506 n_bytes += len0 + len1;
1507 n_packets += is_eop0 + is_eop1;
1520 n_descriptors_left -= 2;
1540 u32 bi_sop0 = is_sop ? bi0 : bi_sop;
1541 u32 bi_sop1 = is_eop0 ? bi1 : bi_sop0;
1558 u32 bi_sop0 = is_sop ? bi0 : bi_sop;
1559 u32 bi_sop1 = is_eop0 ? bi1 : bi_sop0;
1563 to_next[0] = bi_sop0;
1568 to_next, n_left_to_next,
1573 to_next[0] = bi_sop1;
1578 to_next, n_left_to_next,
1587 u8 saved_is_sop = is_sop;
1588 u32 bi_sop_save = bi_sop;
1590 bi_sop = saved_is_sop ? bi0 : bi_sop;
1591 to_next[0] = bi_sop;
1593 n_left_to_next -= is_eop0;
1595 bi_sop = is_eop0 ? bi1 : bi_sop;
1596 to_next[0] = bi_sop;
1598 n_left_to_next -= is_eop1;
1603 (!(next0 == next_index && next1 == next_index)))
1606 to_next -= is_eop0 + is_eop1;
1607 n_left_to_next += is_eop0 + is_eop1;
1610 bi_sop = saved_is_sop ? bi0 : bi_sop_save;
1613 if (next0 != next_index)
1617 to_next[0] = bi_sop;
1619 n_left_to_next -= 1;
1623 bi_sop = is_eop0 ? bi1 : bi_sop;
1626 if (next1 != next_index)
1630 to_next[0] = bi_sop;
1632 n_left_to_next -= 1;
1637 if (is_eop0 && is_eop1 && next0 == next1)
1643 to_next, n_left_to_next);
1650 found_hw_owned_descriptor_x2:
1652 while (n_descriptors_left > 0 && n_left_to_next > 0)
1656 u32 bi0, fi0, len0, l3_offset0, s20, s00, flags0;
1657 u8 is_eop0, error0, next0;
1666 goto found_hw_owned_descriptor_x1;
1692 (xd, s00, s20, &next0, &error0, &flags0);
1694 next0 = is_sop ? next0 : next_index_sop;
1695 next_index_sop = next0;
1697 b0->
flags |= flags0 | (!is_eop0 << VLIB_BUFFER_LOG2_NEXT_PRESENT);
1706 n_packets += is_eop0;
1715 n_descriptors_left -= 1;
1727 bi_sop = is_sop ? bi0 : bi_sop;
1729 if (CLIB_DEBUG > 0 && is_eop0)
1740 to_next[0] = bi_sop;
1745 to_next, n_left_to_next,
1753 to_next[0] = bi_sop;
1755 n_left_to_next -= is_eop0;
1759 if (next0 != next_index && is_eop0)
1765 to_next, n_left_to_next);
1773 found_hw_owned_descriptor_x1:
1774 if (n_descriptors_left > 0)
1780 u32 n_done = n_descriptors - n_descriptors_left;
1782 if (n_trace > 0 && n_done > 0)
1793 _vec_len (d_trace_save) = 0;
1794 _vec_len (d_trace_buffers) = 0;
1806 dq->
rx.n_descriptors_done_this_call = n_done;
1807 dq->
rx.n_descriptors_done_total += n_done;
1808 dq->
rx.is_start_of_packet = is_sop;
1809 dq->
rx.saved_start_of_packet_buffer_index = bi_sop;
1810 dq->
rx.saved_last_buffer_index = bi_last;
1811 dq->
rx.saved_start_of_packet_next_index = next_index_sop;
1812 dq->
rx.next_index = next_index;
1813 dq->
rx.n_bytes += n_bytes;
1827 uword n_packets = 0;
1828 u32 hw_head_index, sw_head_index;
1834 dq->
rx.is_start_of_packet = 1;
1835 dq->
rx.saved_start_of_packet_buffer_index = ~0;
1836 dq->
rx.saved_last_buffer_index = ~0;
1841 dq->
rx.n_descriptors_done_total = 0;
1842 dq->
rx.n_descriptors_done_this_call = 0;
1849 if (hw_head_index == sw_head_index)
1852 if (hw_head_index < sw_head_index)
1858 dq->
rx.n_descriptors_done_this_call);
1860 if (dq->
rx.n_descriptors_done_this_call != n_tried)
1863 if (hw_head_index >= sw_head_index)
1865 u32 n_tried = hw_head_index - sw_head_index;
1869 dq->
rx.n_descriptors_done_this_call);
1883 interface_main.combined_sw_if_counters +
1902 .function = (
char *) __FUNCTION__,.
format =
1903 "ixge %d, %s",.format_args =
"i1t1",.n_enum_strings =
1910 "link status change",
1911 "linksec key exchange",
1912 "manageability event",
1918 "ecc",
"descriptor handler error",
"tcp timer",
"other",},};
1931 uword is_up = (v & (1 << 30)) != 0;
1935 .function = (
char *) __FUNCTION__,.
format =
1936 "ixge %d, link status change 0x%x",.format_args =
"i4i4",};
1943 ed->link_status = v;
1959 u32 bi0, bi1, bi2, bi3;
2001 u32 n_clean, *b, *t, *t0;
2002 i32 n_hw_owned_descriptors;
2003 i32 first_to_clean, last_to_clean;
2009 while ((dq->
head_index == dq->
tx.head_index_write_back[0]) &&
2017 .function = (
char *) __FUNCTION__,.
format =
2018 "ixge %d tx head index race: head %4d, tail %4d, buffs %4d",.format_args
2022 u32 instance, head_index, tail_index, n_buffers_on_ring;
2028 ed->n_buffers_on_ring = dq->
tx.n_buffers_on_ring;
2034 ASSERT (dq->
tx.n_buffers_on_ring >= n_hw_owned_descriptors);
2035 n_clean = dq->
tx.n_buffers_on_ring - n_hw_owned_descriptors;
2041 .function = (
char *) __FUNCTION__,.
format =
2042 "ixge %d tx head index race: head %4d, hw_owned %4d, n_clean %4d, retries %d",.format_args
2046 u32 instance, head_index, n_hw_owned_descriptors, n_clean, retries;
2051 ed->n_hw_owned_descriptors = n_hw_owned_descriptors;
2052 ed->n_clean = n_clean;
2053 ed->retries = hwbp_race;
2068 last_to_clean = (last_to_clean < 0) ? last_to_clean + dq->
n_descriptors :
2071 first_to_clean = (last_to_clean) - (n_clean - 1);
2072 first_to_clean = (first_to_clean < 0) ? first_to_clean + dq->
n_descriptors :
2080 if (first_to_clean > last_to_clean)
2088 if (first_to_clean <= last_to_clean)
2089 t +=
clean_block (b, t, (last_to_clean - first_to_clean) + 1);
2095 ASSERT (dq->
tx.n_buffers_on_ring >= n);
2096 dq->
tx.n_buffers_on_ring -= n;
2111 return i >= 8 && i < 16;
2146 uword n_rx_packets = 0;
2165 return n_rx_packets;
2173 uword n_rx_packets = 0;
2175 if (node->
state == VLIB_NODE_STATE_INTERRUPT)
2182 xd = vec_elt_at_index (xm->devices, i);
2183 n_rx_packets += ixge_device_input (xm, xd, node);
2186 if (! (node->flags & VLIB_NODE_FLAG_SWITCH_FROM_INTERRUPT_TO_POLLING_MODE))
2187 xd->regs->interrupt.enable_write_1_to_set = ~0;
2208 return n_rx_packets;
2221 .name =
"ixge-input",
2225 .state = VLIB_NODE_STATE_DISABLED,
2252 return format (s,
"TenGigabitEthernet%x/%x/%x/%x",
2253 addr->domain, addr->bus, addr->slot, addr->function);
2256 #define IXGE_COUNTER_IS_64_BIT (1 << 0) 2257 #define IXGE_COUNTER_NOT_CLEAR_ON_READ (1 << 1) 2261 #define _64(a,f) IXGE_COUNTER_IS_64_BIT, 2271 static u32 reg_offsets[] = {
2272 #define _(a,f) (a) / sizeof (u32), 2273 #define _64(a,f) _(a,f) 2283 u32 o = reg_offsets[
i];
2295 u32 device_id = va_arg (*args,
u32);
2299 #define _(f,n) case n: t = #f; break; 2307 s =
format (s,
"unknown 0x%x", device_id);
2319 s =
format (s,
"%s", (v & (1 << 30)) ?
"up" :
"down");
2323 "1g",
"10g parallel",
"10g serial",
"autoneg",
2326 "unknown",
"100m",
"1g",
"10g",
2328 s =
format (s,
", mode %s, speed %s",
2329 modes[(v >> 26) & 3], speeds[(v >> 28) & 3]);
2338 u32 dev_instance = va_arg (*args,
u32);
2349 s =
format (s,
"Intel 8259X: id %U\n%Ulink %U",
2369 s =
format (s,
"PHY not found");
2380 s =
format (s,
"\n%U%d unprocessed, %d total buffers on rx queue 0 ring",
2383 s =
format (s,
"\n%U%d buffers in driver rx cache",
2387 s =
format (s,
"\n%U%d buffers on tx queue 0 ring",
2394 static char *names[] = {
2396 #define _64(a,f) _(a,f) 2406 s =
format (s,
"\n%U%-40U%16Ld",
2437 if (node_index == ~0)
2461 #define IXGE_N_BYTES_IN_RX_BUFFER (2048) // DAW-HACK: Set Rx buffer size so all packets < ETH_MTU_SIZE fit in the buffer (i.e. sop & eop for all descriptors). 2507 for (i = 0; i < n_alloc; i++)
2518 dq->
tx.head_index_write_back =
2520 if (!dq->
tx.head_index_write_back)
2559 dr->
tx.head_index_write_back_address[0] = 1 |
a;
2560 dr->
tx.head_index_write_back_address[1] = (
u64) a >> (
u64) 32;
2583 while (!(dr->
control & (1 << 25)))
2610 else if (flags == ETHERNET_INTERFACE_FLAGS_DEFAULT_L3)
2628 const u32 reset_bit = (1 << 26) | (1 << 3);
2633 while (r->
control & reset_bit)
2649 for (i = 0; i < 6; i++)
2650 addr8[i] = addr32[i / 4] >> ((i % 4) * 8);
2686 f64 line_rate_max_pps =
2687 10e9 / (8 * (64 + 20));
2713 uword event_type, *event_data = 0;
2714 f64 timeout, link_debounce_deadline;
2726 link_debounce_deadline = 1e70;
2752 uword is_up = (v & (1 << 30)) != 0;
2758 link_debounce_deadline = 1e70;
2768 _vec_len (event_data) = 0;
2787 .name =
"ixge-process",
2872 ? VLIB_NODE_STATE_POLLING
2873 : VLIB_NODE_STATE_INTERRUPT));
2896 .supported_devices = {
2897 #define _(t,i) { .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = i, }, 2915 r->next_nodes[next] =
name;
2919 clib_warning (
"%s: illegal next %d\n", __FUNCTION__, next);
2926 .version = VPP_BUILD_VER,
2927 .default_disabled = 1,
2928 .description =
"Intel 82599 Family Native Driver (experimental)",
static void ixge_update_counters(ixge_device_t *xd)
#define vec_validate(V, I)
Make sure vector is long enough for given index (no header, unspecified alignment) ...
u32 flags
buffer flags: VLIB_BUFFER_FREE_LIST_INDEX_MASK: bits used to store free list index, VLIB_BUFFER_IS_TRACED: trace this buffer.
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_UDP
#define IXGE_TX_DESCRIPTOR_STATUS0_IS_END_OF_PACKET
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6_EXT
static clib_error_t * ixge_interface_admin_up_down(vnet_main_t *vnm, u32 hw_if_index, u32 flags)
#define IXGE_RX_DESCRIPTOR_STATUS2_ETHERNET_ERROR
static clib_error_t * vlib_pci_intr_enable(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static void ixge_software_firmware_sync_release(ixge_device_t *xd, u32 sw_mask)
ixge_rx_to_hw_descriptor_t rx_to_hw
static void ixge_phy_init(ixge_device_t *xd)
static clib_error_t * vlib_pci_bus_master_enable(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static u32 vlib_get_trace_count(vlib_main_t *vm, vlib_node_runtime_t *rt)
ixge_tx_descriptor_t tx_descriptor_template
static f64 vlib_process_wait_for_event_or_clock(vlib_main_t *vm, f64 dt)
Suspend a cooperative multi-tasking thread Waits for an event, or for the indicated number of seconds...
vl_api_wireguard_peer_flags_t flags
u32 enable_write_1_to_set
static u32 ixge_flag_change(vnet_main_t *vnm, vnet_hw_interface_t *hw, u32 flags)
#define IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR
static void vlib_increment_combined_counter(vlib_combined_counter_main_t *cm, u32 thread_index, u32 index, u64 n_packets, u64 n_bytes)
Increment a combined counter.
u8 runtime_data[0]
Function dependent node-runtime data.
u32 n_descriptors[VLIB_N_RX_TX]
u32 link_status_at_last_link_change
static void vlib_set_next_frame_buffer(vlib_main_t *vm, vlib_node_runtime_t *node, u32 next_index, u32 buffer_index)
vnet_main_t * vnet_get_main(void)
static uword vlib_buffer_get_pa(vlib_main_t *vm, vlib_buffer_t *b)
static void ixge_semaphore_release(ixge_device_t *xd)
static void * vlib_physmem_alloc(vlib_main_t *vm, uword n_bytes)
i16 current_data
signed offset in data[], pre_data[] that we are currently processing.
#define IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED
u32 * descriptor_buffer_indices
static void vlib_error_count(vlib_main_t *vm, uword node_index, uword counter, uword increment)
static void vlib_node_set_interrupt_pending(vlib_main_t *vm, u32 node_index)
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6
clib_memset(h->entries, 0, sizeof(h->entries[0]) *entries)
static f64 vlib_time_now(vlib_main_t *vm)
#define VLIB_NODE_FLAG_TRACE_SUPPORTED
static u8 * format_ixge_link_status(u8 *s, va_list *args)
static clib_error_t * vlib_physmem_last_error(struct vlib_main_t *vm)
static vnet_hw_interface_t * vnet_get_hw_interface(vnet_main_t *vnm, u32 hw_if_index)
u16 current_length
Nbytes between current data and the end of this buffer.
static vlib_node_registration_t ixge_input_node
(constructor) VLIB_REGISTER_NODE (ixge_input_node)
PCI_REGISTER_DEVICE(ixge_pci_device_registration, static)
static uword ixge_rx_queue_no_wrap(ixge_main_t *xm, ixge_device_t *xd, ixge_dma_queue_t *dq, u32 start_descriptor_index, u32 n_descriptors)
static uword sfp_eeprom_is_valid(sfp_eeprom_t *e)
#define vec_add2(V, P, N)
Add N elements to end of vector V, return pointer to new elements in P.
for(i=1;i<=collision_buckets;i++)
#define IXGE_N_BYTES_IN_RX_BUFFER
static void ixge_throttle_queue_interrupt(ixge_regs_t *r, u32 queue_interrupt_index, f64 inter_interrupt_interval_in_secs)
static void ixge_i2c_put_bits(i2c_bus_t *b, int scl, int sda)
u32 per_interface_next_index
static uword ixge_interrupt_is_rx_queue(uword i)
static vnet_sw_interface_t * vnet_get_sw_interface(vnet_main_t *vnm, u32 sw_if_index)
static void ixge_i2c_get_bits(i2c_bus_t *b, int *scl, int *sda)
static void ixge_write_phy_reg(ixge_device_t *xd, u32 dev_type, u32 reg_index, u32 v)
static u8 ixge_counter_flags[]
static vlib_buffer_known_state_t vlib_buffer_is_known(vlib_main_t *vm, u32 buffer_index)
u32 rx_ethernet_address0[16][2]
vlib_error_t * errors
Vector of errors for this node.
static uword ixge_ring_add(ixge_dma_queue_t *q, u32 i0, u32 i1)
u32 * tx_buffers_pending_free
static uword vlib_node_add_next(vlib_main_t *vm, uword node, uword next_node)
#define IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET
#define foreach_set_bit(var, mask, body)
struct ixge_dma_regs_t::@692::@695 tx
static vnet_sw_interface_t * vnet_get_hw_sw_interface(vnet_main_t *vnm, u32 hw_if_index)
static void ixge_rx_next_and_error_from_status_x1(ixge_device_t *xd, u32 s00, u32 s02, u8 *next0, u8 *error0, u32 *flags0)
#define vec_add(V, E, N)
Add N elements to end of vector V (no header, unspecified alignment)
static void vlib_trace_buffer(vlib_main_t *vm, vlib_node_runtime_t *r, u32 next_index, vlib_buffer_t *b, int follow_chain)
static u32 clean_block(u32 *b, u32 *t, u32 n_left)
vlib_pci_dev_handle_t pci_dev_handle
static uword vlib_process_suspend(vlib_main_t *vm, f64 dt)
Suspend a vlib cooperative multi-tasking thread for a period of time.
u32 ixge_read_write_phy_reg(ixge_device_t *xd, u32 dev_type, u32 reg_index, u32 v, u32 is_read)
static uword ixge_rx_queue_to_interrupt(uword i)
ixge_tx_descriptor_t descriptor
static u8 * format_ixge_rx_from_hw_descriptor(u8 *s, va_list *va)
#define vlib_prefetch_buffer_with_index(vm, bi, type)
Prefetch buffer metadata by buffer index The first 64 bytes of buffer contains most header informatio...
#define VLIB_INIT_FUNCTION(x)
static clib_error_t * ixge_sfp_phy_init_from_eeprom(ixge_device_t *xd, u16 sfp_type)
static uword vlib_process_get_events(vlib_main_t *vm, uword **data_vector)
Return the first event type which has occurred and a vector of per-event data of that type...
static void * vlib_physmem_alloc_aligned(vlib_main_t *vm, uword n_bytes, uword alignment)
static void ixge_rx_trace(ixge_main_t *xm, ixge_device_t *xd, ixge_dma_queue_t *dq, ixge_descriptor_t *before_descriptors, u32 *before_buffers, ixge_descriptor_t *after_descriptors, uword n_descriptors)
#define IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED
#define IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR
ixge_dma_regs_t tx_dma[128]
struct ixge_regs_t::@700 xge_mac
#define IXGE_RX_DESCRIPTOR_STATUS2_IS_VLAN
#define vec_elt_at_index(v, i)
Get vector value at index i checking that i is in bounds.
vnet_device_class_t ixge_device_class
static vlib_node_registration_t ixge_process_node
#define vec_resize(V, N)
Resize a vector (no header, unspecified alignment) Add N elements to end of given vector V...
#define vec_end(v)
End (last data address) of vector.
#define clib_error_create(args...)
f64 time_last_stats_update
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_LAYER2
static clib_error_t * ixge_pci_init(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static void ixge_rx_next_and_error_from_status_x2(ixge_device_t *xd, u32 s00, u32 s02, u32 s10, u32 s12, u8 *next0, u8 *error0, u32 *flags0, u8 *next1, u8 *error1, u32 *flags1)
static uword ixge_process(vlib_main_t *vm, vlib_node_runtime_t *rt, vlib_frame_t *f)
vlib_error_t error
Error code for buffers to be enqueued to error handler.
vlib_pci_device_info_t * vlib_pci_get_device_info(vlib_main_t *vm, vlib_pci_addr_t *addr, clib_error_t **error)
static void ixge_sfp_enable_disable_10g(ixge_device_t *xd, uword enable)
static u8 * format_ixge_tx_descriptor(u8 *s, va_list *va)
format_function_t format_vnet_sw_interface_name
#define IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET(l)
static uword ixge_interface_tx(vlib_main_t *vm, vlib_node_runtime_t *node, vlib_frame_t *f)
u16 state
Input node state.
static void ixge_clear_hw_interface_counters(u32 instance)
static void ixge_sfp_device_up_down(ixge_device_t *xd, uword is_up)
format_function_t format_vnet_buffer
#define foreach_ixge_counter
static uword ixge_tx_no_wrap(ixge_main_t *xm, ixge_device_t *xd, ixge_dma_queue_t *dq, u32 *buffers, u32 start_descriptor_index, u32 n_descriptors, ixge_tx_state_t *tx_state)
u64 counters[IXGE_N_COUNTER]
static void vlib_process_signal_event(vlib_main_t *vm, uword node_index, uword type_opaque, uword data)
#define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET
void vlib_pci_set_private_data(vlib_main_t *vm, vlib_pci_dev_handle_t h, uword private_data)
#define IXGE_TX_DESCRIPTOR_STATUS0_IS_ADVANCED
static __clib_warn_unused_result u32 vlib_buffer_alloc(vlib_main_t *vm, u32 *buffers, u32 n_buffers)
Allocate buffers into supplied array.
static void ixge_set_interface_next_node(vnet_main_t *vnm, u32 hw_if_index, u32 node_index)
static u8 * format_ixge_device_id(u8 *s, va_list *args)
u32 vlib_register_node(vlib_main_t *vm, vlib_node_registration_t *r)
#define XGE_PHY_DEV_TYPE_PMA_PMD
#define IXGE_TX_DESCRIPTOR_STATUS0_ADVANCED
format_function_t format_sfp_eeprom
uword vlib_pci_get_private_data(vlib_main_t *vm, vlib_pci_dev_handle_t h)
u32 descriptor_address[2]
static u16 ixge_read_eeprom(ixge_device_t *xd, u32 address)
format_function_t * format_buffer
VNET_DEVICE_CLASS(ixge_device_class)
u32 vlib_pci_dev_handle_t
#define vlib_validate_buffer_enqueue_x1(vm, node, next_index, to_next, n_left_to_next, bi0, next0)
Finish enqueueing one buffer forward in the graph.
#define vlib_get_next_frame(vm, node, next_index, vectors, n_vectors_left)
Get pointer to next frame vector data by (vlib_node_runtime_t, next_index).
u32 software_firmware_sync
static void ixge_sfp_phy_init(ixge_device_t *xd)
vlib_node_runtime_t * node
#define IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE
u32 auto_negotiation_control2
u8 * format_ethernet_header_with_length(u8 *s, va_list *args)
ixge_tx_descriptor_t * start_of_packet_descriptor
static ixge_dma_regs_t * get_dma_regs(ixge_device_t *xd, vlib_rx_or_tx_t rt, u32 qi)
static u8 * format_ixge_tx_dma_trace(u8 *s, va_list *va)
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4
#define VLIB_REGISTER_NODE(x,...)
static void vlib_buffer_free_no_next(vlib_main_t *vm, u32 *buffers, u32 n_buffers)
Free buffers, does not free the buffer chain for each buffer.
#define XGE_PHY_DEV_TYPE_PHY_XS
u32 status_write_1_to_set
static uword ixge_interrupt_tx_queue(uword i)
#define CLIB_PREFETCH(addr, size, type)
sll srl srl sll sra u16x4 i
u8 * vlib_validate_buffer(vlib_main_t *vm, u32 bi, uword follow_buffer_next)
#define IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET(s)
#define clib_warning(format, args...)
static vlib_node_runtime_t * vlib_node_get_runtime(vlib_main_t *vm, u32 node_index)
Get node runtime by node index.
void(* get_bits)(struct i2c_bus_t *b, int *scl, int *sda)
#define ETHERNET_INTERFACE_FLAG_ACCEPT_ALL
static u8 * format_ixge_device_name(u8 *s, va_list *args)
#define IXGE_TX_DESCRIPTOR_STATUS0_INSERT_FCS
void vlib_put_next_frame(vlib_main_t *vm, vlib_node_runtime_t *r, u32 next_index, u32 n_vectors_left)
Release pointer to next frame vector data.
#define ELOG_TYPE_DECLARE(f)
static uword ixge_interrupt_rx_queue(uword i)
static uword round_pow2(uword x, uword pow2)
void vlib_i2c_init(i2c_bus_t *b)
vlib_main_t vlib_node_runtime_t * node
vlib_pci_addr_t * vlib_pci_get_addr(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static u8 * format_ixge_rx_dma_trace(u8 *s, va_list *va)
static char * ixge_error_strings[]
u16 cached_next_index
Next frame index that vector arguments were last enqueued to last time this node ran.
#define IXGE_COUNTER_NOT_CLEAR_ON_READ
manual_print typedef address
u8 pre_data[VLIB_BUFFER_PRE_DATA_SIZE]
Space for inserting data before buffer start.
ixge_pci_device_id_t device_id
ixge_descriptor_t * descriptors
static void ixge_tx_queue(ixge_main_t *xm, ixge_device_t *xd, u32 queue_index)
u32 auto_negotiation_control
#define clib_error_report(e)
struct ixge_dma_queue_t::@721::@723 tx
static void vlib_node_set_state(vlib_main_t *vm, u32 node_index, vlib_node_state_t new_state)
Set node dispatch state.
static vlib_main_t * vlib_get_main(void)
static void ixge_semaphore_get(ixge_device_t *xd)
static void ixge_interrupt(ixge_main_t *xm, ixge_device_t *xd, u32 i)
static uword ixge_tx_descriptor_matches_template(ixge_main_t *xm, ixge_tx_descriptor_t *d)
static uword ixge_tx_queue_to_interrupt(uword i)
void vlib_i2c_read_eeprom(i2c_bus_t *bus, u8 i2c_addr, u16 start_addr, u16 length, u8 *data)
void(* put_bits)(struct i2c_bus_t *b, int scl, int sda)
struct ixge_regs_t::@698 interrupt
struct _vlib_node_registration vlib_node_registration_t
static void ixge_device_init(ixge_main_t *xm)
static void ixge_software_firmware_sync(ixge_device_t *xd, u32 sw_mask)
static u64 vlib_physmem_get_pa(vlib_main_t *vm, void *mem)
ixge_tx_descriptor_t tx_descriptor_template_mask
#define IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED
void ixge_set_next_node(ixge_rx_next_t next, char *name)
ixge_dma_queue_t * dma_queues[VLIB_N_RX_TX]
static uword ixge_ring_sub(ixge_dma_queue_t *q, u32 i0, u32 i1)
static void ixge_tx_trace(ixge_main_t *xm, ixge_device_t *xd, ixge_dma_queue_t *dq, ixge_tx_state_t *tx_state, ixge_tx_descriptor_t *descriptors, u32 *buffers, uword n_descriptors)
#define vec_len(v)
Number of elements in vector (rvalue-only, NULL tolerant)
u32 next_buffer
Next buffer for this linked-list of buffers.
clib_error_t * ethernet_register_interface(vnet_main_t *vnm, u32 dev_class_index, u32 dev_instance, const u8 *address, u32 *hw_if_index_return, ethernet_flag_change_function_t flag_change)
clib_error_t * vnet_hw_interface_set_flags(vnet_main_t *vnm, u32 hw_if_index, vnet_hw_interface_flags_t flags)
#define VLIB_BUFFER_TRACE_TRAJECTORY_INIT(b)
static uword ixge_interrupt_is_tx_queue(uword i)
VLIB buffer representation.
#define IXGE_COUNTER_IS_64_BIT
static void * vlib_frame_vector_args(vlib_frame_t *f)
Get pointer to frame vector data.
static uword ixge_device_input(ixge_main_t *xm, ixge_device_t *xd, vlib_node_runtime_t *node)
static uword ixge_input(vlib_main_t *vm, vlib_node_runtime_t *node, vlib_frame_t *f)
u32 n_descriptors_per_cache_line
clib_error_t * vlib_pci_map_region(vlib_main_t *vm, vlib_pci_dev_handle_t h, u32 resource, void **result)
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4_EXT
u16 n_packet_bytes_this_descriptor
static uword ixge_rx_queue(ixge_main_t *xm, ixge_device_t *xd, vlib_node_runtime_t *node, u32 queue_index)
#define XGE_PHY_CONTROL_RESET
static uword vlib_in_process_context(vlib_main_t *vm)
#define IXGE_HWBP_RACE_ELOG
static int vlib_i2c_bus_timed_out(i2c_bus_t *bus)
ixge_dma_regs_t rx_dma0[64]
static void ixge_pci_intr_handler(vlib_main_t *vm, vlib_pci_dev_handle_t h)
#define vec_foreach(var, vec)
Vector iterator.
#define IXGE_RX_DESCRIPTOR_STATUS0_IS_TCP
clib_error_t * ixge_init(vlib_main_t *vm)
u16 flags
Copy of main node flags.
#define CLIB_MEMORY_BARRIER()
void * vlib_add_trace(vlib_main_t *vm, vlib_node_runtime_t *r, vlib_buffer_t *b, u32 n_data_bytes)
static void ixge_sfp_enable_disable_laser(ixge_device_t *xd, uword enable)
format_function_t format_vlib_pci_link_speed
static void vlib_set_trace_count(vlib_main_t *vm, vlib_node_runtime_t *rt, u32 count)
u32 status_write_1_to_clear
#define VLIB_NODE_FLAG_TRACE
#define IXGE_TX_DESCRIPTOR_STATUS0_REPORT_STATUS
#define CLIB_CACHE_LINE_BYTES
static u8 * format_ixge_device(u8 *s, va_list *args)
static u32 ixge_read_phy_reg(ixge_device_t *xd, u32 dev_type, u32 reg_index)
static clib_error_t * ixge_dma_init(ixge_device_t *xd, vlib_rx_or_tx_t rt, u32 queue_index)
static vlib_buffer_t * vlib_get_buffer(vlib_main_t *vm, u32 buffer_index)
Translate buffer index into buffer pointer.
u64 counters_last_clear[IXGE_N_COUNTER]
ixge_dma_regs_t rx_dma1[64]
ixge_rx_from_hw_descriptor_t rx_from_hw
#define VLIB_NODE_FLAG_SWITCH_FROM_POLLING_TO_INTERRUPT_MODE
#define foreach_ixge_error
struct ixge_dma_queue_t::@721::@724 rx
#define IXGE_TX_DESCRIPTOR_STATUS1_DONE
#define IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR