17 #include <sys/ioctl.h> 28 #define PCI_VENDOR_ID_VIRTIO 0x1af4 29 #define PCI_DEVICE_ID_VIRTIO_NIC 0x1000 31 #define PCI_DEVICE_ID_VIRTIO_NIC_MODERN 0x1041 33 #define PCI_CAPABILITY_LIST 0x34 34 #define PCI_CAP_ID_VNDR 0x09 35 #define PCI_CAP_ID_MSIX 0x11 37 #define PCI_MSIX_ENABLE 0x8000 60 u16 max_queue_pairs = 1;
68 if (max_queue_pairs < 1 || max_queue_pairs > 0x8000)
70 " should be in range [1, 0x8000]",
132 vif->
flags |= VIRTIO_IF_FLAG_ADMIN_UP;
138 vif->
flags &= ~VIRTIO_IF_FLAG_ADMIN_UP;
161 for (; line < vif->
num_rxqs; line++)
177 struct status_struct *status_entry;
178 static struct status_struct status_array[] = {
179 #define _(s,b) { .str = #s, .bit = b, }, 187 status_entry = (
struct status_struct *) &status_array;
188 while (status_entry->str)
190 if (vif->
status & status_entry->bit)
206 u16 used, next, avail;
227 d->
len =
sizeof (virtio_net_ctrl_hdr_t);
230 next = (next + 1) & mask;
234 d = &vring->
desc[next];
239 next = (next + 1) & mask;
243 d = &vring->
desc[next];
248 next = (next + 1) & mask;
356 int csum_offload_enabled)
380 else if (csum_offload_enabled
435 if (qsz < 64 || qsz > 4096)
453 queue_size = vif->
virtio_pci_func->get_queue_size (vm, vif, queue_num);
460 if (queue_size > 32768)
485 vring->
size = queue_size;
509 queue_size = vif->
virtio_pci_func->get_queue_size (vm, vif, queue_num);
516 if (queue_size > 32768)
565 vring->
size = queue_size;
608 if (req_features == 0)
610 req_features = supported_features;
652 vif->
virtio_pci_func->set_status (vm, vif, VIRTIO_CONFIG_STATUS_DRIVER);
658 if ((status & VIRTIO_CONFIG_STATUS_ACK)
659 && (status & VIRTIO_CONFIG_STATUS_DRIVER))
672 u8 pos, common_cfg = 0, notify = 0, dev_cfg = 0, isr = 0, pci_cfg = 0;
679 "error in reading capabilty list position");
688 "error in reading the capability at", pos);
690 "error in reading the capability at [%2x]",
696 u16 flags, table_size, table_size_mask = 0x07FF;
702 "error in reading the capability at [%2x]",
705 table_size = flags & table_size_mask;
707 "msix interrupt vector table-size", table_size);
726 "skipping non VNDR cap id:", cap.
cap_vndr);
731 "[%4x] cfg type: %u, bar: %u, offset: %04x, len: %u",
734 if (cap.
bar >= 0 && cap.
bar <= 5)
783 if (common_cfg == 0 || notify == 0 || dev_cfg == 0 || isr == 0)
816 args->
rv = VNET_API_ERROR_UNSUPPORTED;
823 args->
rv = VNET_API_ERROR_INIT_FAILED;
835 "support VIRTIO_RING_F_INDIRECT_DESC features");
840 "support VIRTIO_NET_F_MRG_RXBUF features");
848 VIRTIO_CONFIG_STATUS_FEATURES_OK);
850 if (!(status & VIRTIO_CONFIG_STATUS_FEATURES_OK))
852 args->
rv = VNET_API_ERROR_UNSUPPORTED;
854 "error encountered: Device doesn't support requested features");
856 "Device doesn't support requested features");
867 rnd = (
u32) (now * 1e6);
870 memcpy (vif->
mac_addr + 2, &rnd, sizeof (rnd));
883 args->
rv = VNET_API_ERROR_EXCEEDED_NUMBER_OF_RANGES_CAPACITY;
892 "error MSIX lines (%u) <= Number of RXQs (%u)",
895 "error MSIX lines (%u) <= Number of RXQs (%u)",
905 args->
rv = VNET_API_ERROR_INIT_FAILED;
930 "no VPP worker thread is available");
936 args->
rv = VNET_API_ERROR_INIT_FAILED;
994 RX_QUEUE (i),
"msix vector is set at", j);
1002 vif->
virtio_pci_func->set_status (vm, vif, VIRTIO_CONFIG_STATUS_DRIVER_OK);
1016 u32 interrupt_count = 0;
1020 if (vif->pci_addr.as_u32 == args->addr)
1022 args->rv = VNET_API_ERROR_ADDRESS_IN_USE;
1024 clib_error_return (error,
"PCI address in use");
1025 vlib_log (VLIB_LOG_LEVEL_ERR, vim->log_default,
"%U: %s",
1026 format_vlib_pci_addr, &args->addr,
1027 " PCI address in use");
1034 vif->dev_instance = vif - vim->interfaces;
1035 vif->per_interface_next_index = ~0;
1036 vif->pci_addr.as_u32 = args->addr;
1040 virtio_pci_device_ids, &
h)))
1042 args->rv = VNET_API_ERROR_INVALID_INTERFACE;
1046 vlib_log (VLIB_LOG_LEVEL_ERR, vim->log_default,
"%U: %s",
1048 "error encountered on pci device open");
1052 vif->pci_dev_handle =
h;
1055 vif->type = VIRTIO_IF_TYPE_PCI;
1064 for (
u32 i = 0; i <= 5; i++)
1085 if (interrupt_count > 1)
1090 args->rv = VNET_API_ERROR_INVALID_REGISTRATION;
1092 "error encountered on pci register msix handler 0");
1100 args->rv = VNET_API_ERROR_INVALID_REGISTRATION;
1102 "error encountered on pci register msix handler 1");
1111 vif->support_int_mode = 1;
1114 else if (interrupt_count == 1)
1123 "error encountered on pci register interrupt handler");
1126 vif->support_int_mode = 1;
1135 vif->support_int_mode = 0;
1153 vif->dev_instance, vif->mac_addr,
1159 args->rv = VNET_API_ERROR_INVALID_REGISTRATION;
1161 "error encountered on ethernet register interface");
1184 vif->flags |= VIRTIO_IF_FLAG_ADMIN_UP;
1192 args->checksum_offload_enabled);
1205 args->rv = VNET_API_ERROR_INVALID_INTERFACE;
1206 args->error = error;
1216 if (vif->
type != VIRTIO_IF_TYPE_PCI)
1217 return VNET_API_ERROR_INVALID_INTERFACE;
1287 memset (vif, 0,
sizeof (*vif));
1296 int checksum_offload_enabled,
1297 int offloads_disabled)
1299 if (vif->
type != VIRTIO_IF_TYPE_PCI)
1300 return VNET_API_ERROR_INVALID_INTERFACE;
1304 else if (checksum_offload_enabled)
1306 else if (offloads_disabled)
gro_flow_table_t * flow_table
vlib_node_registration_t virtio_input_node
(constructor) VLIB_REGISTER_NODE (virtio_input_node)
static uword vlib_buffer_get_current_pa(vlib_main_t *vm, vlib_buffer_t *b)
#define vec_foreach_index(var, v)
Iterate over vector indices.
static int virtio_pci_disable_offload(vlib_main_t *vm, virtio_if_t *vif)
static clib_error_t * vlib_pci_intr_enable(vlib_main_t *vm, vlib_pci_dev_handle_t h)
void virtio_set_net_hdr_size(virtio_if_t *vif)
clib_error_t * virtio_pci_vring_init(vlib_main_t *vm, virtio_if_t *vif, u16 queue_num)
static u32 virtio_pci_flag_change(vnet_main_t *vnm, vnet_hw_interface_t *hw, u32 flags)
static clib_error_t * vlib_pci_bus_master_enable(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static void * vlib_physmem_alloc_aligned_on_numa(vlib_main_t *vm, uword n_bytes, uword alignment, u32 numa_node)
#define VIRTIO_PCI_CAP_ISR_CFG
vl_api_wireguard_peer_flags_t flags
static void vlib_buffer_free(vlib_main_t *vm, u32 *buffers, u32 n_buffers)
Free buffers Frees the entire buffer chain for each buffer.
void ethernet_delete_interface(vnet_main_t *vnm, u32 hw_if_index)
vnet_main_t * vnet_get_main(void)
i16 current_data
signed offset in data[], pre_data[] that we are currently processing.
void vlib_pci_device_close(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static void virtio_pci_irq_queue_handler(vlib_main_t *vm, vlib_pci_dev_handle_t h, u16 line)
#define CLIB_MEMORY_STORE_BARRIER()
vring_used_elem_t ring[0]
clib_memset(h->entries, 0, sizeof(h->entries[0]) *entries)
static f64 vlib_time_now(vlib_main_t *vm)
u32 vlib_pci_get_num_msix_interrupts(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static clib_error_t * vlib_physmem_last_error(struct vlib_main_t *vm)
const virtio_pci_func_t * virtio_pci_func
static clib_error_t * vlib_pci_intr_disable(vlib_main_t *vm, vlib_pci_dev_handle_t h)
static clib_error_t * virtio_pci_device_init(vlib_main_t *vm, virtio_if_t *vif, virtio_pci_create_if_args_t *args, void **bar)
static vnet_hw_interface_t * vnet_get_hw_interface(vnet_main_t *vnm, u32 hw_if_index)
vnet_device_class_t virtio_device_class
static heap_elt_t * last(heap_header_t *h)
void virtio_vring_set_numa_node(vlib_main_t *vm, virtio_if_t *vif, u32 idx)
#define STRUCT_OFFSET_OF(t, f)
clib_error_t * vlib_pci_enable_msix_irq(vlib_main_t *vm, vlib_pci_dev_handle_t h, u16 start, u16 count)
#define vec_validate_aligned(V, I, A)
Make sure vector is long enough for given index (no header, specified alignment)
#define pool_get(P, E)
Allocate an object E from a pool P (unspecified alignment).
static int virtio_pci_enable_gso(vlib_main_t *vm, virtio_if_t *vif)
#define VIRTIO_NET_CTRL_GUEST_OFFLOADS
static void virtio_pci_set_mac(vlib_main_t *vm, virtio_if_t *vif)
void virtio_pci_create_if(vlib_main_t *vm, virtio_pci_create_if_args_t *args)
#define VIRTIO_FEATURE(X)
static void clib_spinlock_free(clib_spinlock_t *p)
static vnet_sw_interface_t * vnet_get_hw_sw_interface(vnet_main_t *vnm, u32 hw_if_index)
#define clib_memcpy(d, s, n)
static void virtio_pci_irq_handler(vlib_main_t *vm, vlib_pci_dev_handle_t h)
const virtio_pci_func_t virtio_pci_legacy_func
clib_error_t * vlib_pci_read_write_config(vlib_main_t *vm, vlib_pci_dev_handle_t h, vlib_read_or_write_t read_or_write, uword address, void *data, u32 n_bytes)
#define VIRTIO_PCI_CAP_COMMON_CFG
int virtio_pci_reset_device(vlib_main_t *vm, virtio_if_t *vif)
static u8 virtio_pci_queue_size_valid(u16 qsz)
#define pool_foreach(VAR, POOL, BODY)
Iterate through pool.
#define virtio_log_error(vif, f,...)
#define PCI_DEVICE_ID_VIRTIO_NIC
#define TX_QUEUE_ACCESS(X)
u32 notify_off_multiplier
void device_status(vlib_main_t *vm, virtio_if_t *vif)
static_always_inline void vnet_device_input_set_interrupt_pending(vnet_main_t *vnm, u32 hw_if_index, u16 queue_id)
static void virtio_negotiate_features(vlib_main_t *vm, virtio_if_t *vif, u64 req_features)
vnet_hw_interface_flags_t flags
void virtio_free_rx_buffers(vlib_main_t *vm, virtio_vring_t *vring)
#define vec_elt_at_index(v, i)
Get vector value at index i checking that i is in bounds.
#define clib_error_return(e, args...)
#define VIRTIO_PCI_CAP_NOTIFY_CFG
#define virtio_log_warning(vif, f,...)
#define VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET
static void clib_spinlock_init(clib_spinlock_t *p)
#define pool_elt_at_index(p, i)
Returns pointer to element at given index.
#define VIRTIO_MSI_NO_VECTOR
void vlib_pci_set_private_data(vlib_main_t *vm, vlib_pci_dev_handle_t h, uword private_data)
static __clib_warn_unused_result u32 vlib_buffer_alloc(vlib_main_t *vm, u32 *buffers, u32 n_buffers)
Allocate buffers into supplied array.
static_always_inline u16 vring_size(u32 num, u32 align)
#define VIRTIO_PCI_ISR_CONFIG
static void * vlib_buffer_get_current(vlib_buffer_t *b)
Get pointer to current data to process.
#define pool_put(P, E)
Free an object E in pool P.
clib_error_t * vlib_pci_register_msix_handler(vlib_main_t *vm, vlib_pci_dev_handle_t h, u32 start, u32 count, pci_msix_handler_function_t *msix_handler)
uword vlib_pci_get_private_data(vlib_main_t *vm, vlib_pci_dev_handle_t h)
u32 vlib_pci_dev_handle_t
void virtio_pci_read_device_feature(vlib_main_t *vm, virtio_if_t *vif)
virtio_net_ctrl_hdr_t ctrl
static clib_error_t * virtio_pci_get_max_virtqueue_pairs(vlib_main_t *vm, virtio_if_t *vif)
#define PCI_CAPABILITY_LIST
int virtio_pci_enable_disable_offloads(vlib_main_t *vm, virtio_if_t *vif, int gso_enabled, int checksum_offload_enabled, int offloads_disabled)
#define virtio_log_debug(vif, f,...)
u8 * format_vlib_pci_addr(u8 *s, va_list *va)
#define VIRTIO_PCI_VRING_ALIGN
virtio_vring_t * rxq_vrings
u32 vlib_pci_get_numa_node(vlib_main_t *vm, vlib_pci_dev_handle_t h)
#define VIRTIO_PCI_ISR_INTR
static void vlib_physmem_free(vlib_main_t *vm, void *p)
#define VIRTIO_RING_FLAG_MASK_INT
sll srl srl sll sra u16x4 i
#define vec_free(V)
Free vector's memory (no header).
#define VIRTIO_NET_CTRL_MQ
#define clib_warning(format, args...)
static u16 virtio_pci_is_link_up(vlib_main_t *vm, virtio_if_t *vif)
void vlib_log(vlib_log_level_t level, vlib_log_class_t class, char *fmt,...)
static_always_inline void vring_init(vring_t *vr, u32 num, void *p, u32 align)
clib_error_t * virtio_pci_control_vring_init(vlib_main_t *vm, virtio_if_t *vif, u16 queue_num)
static uword round_pow2(uword x, uword pow2)
int virtio_pci_delete_if(vlib_main_t *vm, virtio_if_t *vif)
void virtio_free_used_desc(vlib_main_t *vm, virtio_vring_t *vring)
#define PCI_DEVICE_ID_VIRTIO_NIC_MODERN
static int virtio_pci_offloads(vlib_main_t *vm, virtio_if_t *vif, int gso_enabled, int csum_offload_enabled)
void vnet_hw_interface_assign_rx_thread(vnet_main_t *vnm, u32 hw_if_index, u16 queue_id, uword thread_index)
void vlib_cli_output(vlib_main_t *vm, char *fmt,...)
clib_error_t * virtio_pci_read_caps(vlib_main_t *vm, virtio_if_t *vif, void **bar)
static int virtio_pci_send_ctrl_msg(vlib_main_t *vm, virtio_if_t *vif, virtio_ctrl_msg_t *data, u32 len)
static int virtio_pci_enable_checksum_offload(vlib_main_t *vm, virtio_if_t *vif)
const virtio_pci_func_t virtio_pci_modern_func
clib_error_t * vlib_pci_register_intx_handler(vlib_main_t *vm, vlib_pci_dev_handle_t h, pci_intx_handler_function_t *intx_handler)
#define VRING_DESC_F_NEXT
virtio_net_ctrl_ack_t status
virtio_main_t virtio_main
static uword is_pow2(uword x)
#define RX_QUEUE_ACCESS(X)
#define VIRTIO_PCI_CAP_DEVICE_CFG
clib_error_t * ethernet_register_interface(vnet_main_t *vnm, u32 dev_class_index, u32 dev_instance, const u8 *address, u32 *hw_if_index_return, ethernet_flag_change_function_t flag_change)
clib_error_t * vnet_hw_interface_set_flags(vnet_main_t *vnm, u32 hw_if_index, vnet_hw_interface_flags_t flags)
VLIB buffer representation.
static void virtio_pci_irq_config_handler(vlib_main_t *vm, vlib_pci_dev_handle_t h, u16 line)
#define clib_error_free(e)
#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET
clib_error_t * vlib_pci_io_region(vlib_main_t *vm, vlib_pci_dev_handle_t h, u32 resource)
clib_error_t * vlib_pci_map_region(vlib_main_t *vm, vlib_pci_dev_handle_t h, u32 resource, void **result)
int vnet_hw_interface_unassign_rx_thread(vnet_main_t *vnm, u32 hw_if_index, u16 queue_id)
virtio_vring_t * cxq_vring
static u32 random_u32(u32 *seed)
32-bit random number generator
static vlib_thread_main_t * vlib_get_thread_main()
#define CLIB_MEMORY_BARRIER()
int vnet_hw_interface_set_rx_mode(vnet_main_t *vnm, u32 hw_if_index, u16 queue_id, vnet_hw_interface_rx_mode mode)
#define VIRTIO_PCI_CAP_PCI_CFG
#define CLIB_CACHE_LINE_BYTES
#define PCI_VENDOR_ID_VIRTIO
#define VRING_DESC_F_WRITE
clib_error_t * vlib_pci_device_open(vlib_main_t *vm, vlib_pci_addr_t *addr, pci_device_id_t ids[], vlib_pci_dev_handle_t *handle)
static u32 virtio_pci_get_mac(vlib_main_t *vm, virtio_if_t *vif)
static vlib_buffer_t * vlib_get_buffer(vlib_main_t *vm, u32 buffer_index)
Translate buffer index into buffer pointer.
static void vnet_hw_interface_set_input_node(vnet_main_t *vnm, u32 hw_if_index, u32 node_index)
static int virtio_pci_enable_multiqueue(vlib_main_t *vm, virtio_if_t *vif, u16 num_queues)
virtio_vring_t * txq_vrings
static_always_inline void virtio_kick(vlib_main_t *vm, virtio_vring_t *vring, virtio_if_t *vif)
static_always_inline void clib_memset_u32(void *p, u32 val, uword count)