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Vector Packet Processing
core.c
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1 /*
2  * Copyright (c) 2020 Cisco and/or its affiliates.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at:
6  *
7  * http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #include <vnet/vnet.h>
17 #include <perfmon/perfmon.h>
18 #include <perfmon/intel/core.h>
19 #include <linux/perf_event.h>
20 
21 static perfmon_event_t events[] = {
22 #define _(event, umask, edge, any, inv, cmask, n, suffix, desc) \
23  [INTEL_CORE_E_##n##_##suffix] = { .type = PERF_TYPE_RAW, \
24  .config = PERF_INTEL_CODE ( \
25  event, umask, edge, any, inv, cmask), \
26  .name = #n "." #suffix, \
27  .description = desc, \
28  .exclude_kernel = 1 },
29 
31 #undef _
32 };
33 
34 u8 *
35 format_intel_core_config (u8 *s, va_list *args)
36 {
37  u64 config = va_arg (*args, u64);
38  u8 v;
39 
40  s = format (s, "event=0x%02x, umask=0x%02x", config & 0xff,
41  (config >> 8) & 0xff);
42 
43  if ((v = (config >> 18) & 1))
44  s = format (s, ", edge=%u", v);
45 
46  if ((v = (config >> 19) & 1))
47  s = format (s, ", pc=%u", v);
48 
49  if ((v = (config >> 21) & 1))
50  s = format (s, ", any=%u", v);
51 
52  if ((v = (config >> 23) & 1))
53  s = format (s, ", inv=%u", v);
54 
55  if ((v = (config >> 24) & 0xff))
56  s = format (s, ", cmask=0x%02x", v);
57 
58  return s;
59 }
60 
61 static clib_error_t *
63 {
64  u32 eax, ebx, ecx, edx;
65  if (__get_cpuid (0, &eax, &ebx, &ecx, &edx) == 0)
66  return clib_error_return (0, "unknown CPU (missing cpuid)");
67 
68  // GenuineIntel
69  if (ebx != 0x756e6547 || ecx != 0x6c65746e || edx != 0x49656e69)
70  return clib_error_return (0, "not a IA-32 CPU");
71  return 0;
72 }
73 
74 PERFMON_REGISTER_SOURCE (intel_core) = {
75  .name = "intel-core",
76  .description = "intel arch core events",
77  .events = events,
78  .n_events = ARRAY_LEN (events),
79  .init_fn = intel_core_init,
80  .format_config = format_intel_core_config,
81 };
perfmon_event_t
Definition: perfmon.h:43
clib_error_return
#define clib_error_return(e, args...)
Definition: error.h:99
vm
vlib_main_t * vm
X-connect all packets from the HOST to the PHY.
Definition: nat44_ei.c:3047
foreach_perf_intel_core_event
#define foreach_perf_intel_core_event
Definition: core.h:25
format_intel_core_config
u8 * format_intel_core_config(u8 *s, va_list *args)
Definition: core.c:35
perfmon_source
Definition: perfmon.h:81
ARRAY_LEN
#define ARRAY_LEN(x)
Definition: clib.h:70
events
static perfmon_event_t events[]
Definition: core.c:21
src
vl_api_address_t src
Definition: gre.api:54
u64
unsigned long u64
Definition: types.h:89
format
description fragment has unexpected format
Definition: map.api:433
u32
unsigned int u32
Definition: types.h:88
core.h
vlib_main_t
Definition: main.h:102
u8
unsigned char u8
Definition: types.h:56
clib_error_t
Definition: clib_error.h:21
vnet.h
PERFMON_REGISTER_SOURCE
PERFMON_REGISTER_SOURCE(intel_core)
intel_core_init
static clib_error_t * intel_core_init(vlib_main_t *vm, perfmon_source_t *src)
Definition: core.c:62