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Vector Packet Processing
vector_altivec.h
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/*
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* Copyright (c) 2015 Cisco and/or its affiliates.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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Copyright (c) 2009 Eliot Dresselhaus
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef included_vector_altivec_h
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#define included_vector_altivec_h
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/* 128 bit shifts. */
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#define _(t,ti,lr,f) \
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always_inline t t##_##lr (t x, t y) \
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{ return (t) __builtin_altivec_##f ((ti) x, (ti) y); } \
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\
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always_inline t t##_i##lr (t x, int i) \
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{ \
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t j = {i,i,i,i}; \
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return t##_##lr (x, j); \
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}
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_(
u16x8
,
i16x8
, shift_left, vslh);
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_(
u32x4
,
i32x4
, shift_left, vslw);
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_(
u16x8
,
i16x8
, shift_right, vsrh);
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_(
u32x4
,
i32x4
, shift_right, vsrw);
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_(
i16x8
,
i16x8
, shift_right, vsrah);
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_(
i32x4
,
i32x4
, shift_right, vsraw);
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_(
u16x8
,
i16x8
,
rotate_left
, vrlh);
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_(
i16x8
,
i16x8
,
rotate_left
, vrlh);
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_(
u32x4
,
i32x4
,
rotate_left
, vrlw);
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_(
i32x4
,
i32x4
,
rotate_left
, vrlw);
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#undef _
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#define _(t,it,lr,f) \
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always_inline t t##_word_shift_##lr (t x, int n_words) \
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{ \
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i32x4 n_bits = {0,0,0,n_words * BITS (it)}; \
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return (t) __builtin_altivec_##f ((i32x4) x, n_bits); \
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}
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_(
u32x4
,
u32
,
left
, vslo)
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_(
i32x4
,
i32
,
left
, vslo)
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_(
u32x4
,
u32
,
right
, vsro)
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_(
i32x4
,
i32
,
right
, vsro)
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_(
u16x8
,
u16
,
left
, vslo)
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_(
i16x8
,
i16
,
left
, vslo)
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_(
u16x8
,
u16
,
right
, vsro) _(
i16x8
,
i16
,
right
, vsro)
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#undef _
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always_inline
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u32
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u32x4_get0
(
u32x4
x)
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{
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u32x4_union_t y;
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y.as_u32x4 = x;
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return
y.as_u32[3];
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}
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/* Interleave. */
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#define _(t,it,lh,f) \
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always_inline t t##_interleave_##lh (t x, t y) \
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{ return (t) __builtin_altivec_##f ((it) x, (it) y); }
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_(
u32x4
,
i32x4
,
lo
, vmrglw)
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_(
i32x4
,
i32x4
,
lo
, vmrglw)
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_(
u16x8
,
i16x8
,
lo
, vmrglh)
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_(
i16x8
,
i16x8
,
lo
, vmrglh)
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_(
u32x4
,
i32x4
,
hi
, vmrghw)
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_(
i32x4
,
i32x4
,
hi
, vmrghw)
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_(
u16x8
,
i16x8
,
hi
, vmrghh) _(
i16x8
,
i16x8
,
hi
, vmrghh)
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#undef _
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/* Unaligned loads/stores. */
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#ifndef __cplusplus
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#define _(t) \
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always_inline void t##_store_unaligned (t x, t * a) \
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{ clib_mem_unaligned (a, t) = x; } \
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always_inline t t##_load_unaligned (t * a) \
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{ return clib_mem_unaligned (a, t); }
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_(
u8x16
) _(
u16x8
) _(
u32x4
) _(
u64x2
) _(i8x16) _(
i16x8
) _(
i32x4
) _(
i64x2
)
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#undef _
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#endif
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#define _signed_binop(n,m,f,g) \
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/* Unsigned */
\
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always_inline u##n##x##m \
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u##n##x##m##_##f (u##n##x##m x, u##n##x##m y) \
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{ return (u##n##x##m) __builtin_altivec_##g ((i##n##x##m) x, (i##n##x##m) y); } \
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\
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/* Signed */
\
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always_inline i##n##x##m \
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i##n##x##m##_##f (i##n##x##m x, i##n##x##m y) \
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{ return (i##n##x##m) __builtin_altivec_##g ((i##n##x##m) x, (i##n##x##m) y); }
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/* Compare operations. */
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_signed_binop (16, 8,
is_equal
, vcmpequh)
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_signed_binop (32, 4,
is_equal
, vcmpequw)
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#undef _signed_binop
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always_inline
u16x8
u16x8_is_zero (
u16x8
x)
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{
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u16x8
zero = { 0 };
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return
u16x8_is_equal (x, zero);
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}
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always_inline
u32
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u32x4_zero_byte_mask
(
u32x4
x)
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{
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u32x4
cmp = u32x4_is_zero (x);
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u32x4
tmp
= { 0x000f, 0x00f0, 0x0f00, 0xf000, };
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cmp &=
tmp
;
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cmp |=
u32x4_word_shift_right
(cmp, 2);
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cmp |=
u32x4_word_shift_right
(cmp, 1);
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return
u32x4_get0
(cmp);
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}
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#endif
/* included_vector_altivec_h */
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/*
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* fd.io coding-style-patch-verification: ON
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*
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* Local Variables:
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* eval: (c-set-style "gnu")
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* End:
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*/
tmp
u32 * tmp
Definition:
interface_output.c:1078
u32x4_get0
vslo vsro vslo static vsro u32 u32x4_get0(u32x4 x)
Definition:
vector_altivec.h:82
is_equal
is_equal
Definition:
vector_altivec.h:123
u16
unsigned short u16
Definition:
types.h:57
u64x2
epu8_epi32 epu16_epi32 u64x2
Definition:
vector_sse42.h:641
u32x4_zero_byte_mask
static u32 u32x4_zero_byte_mask(u32x4 x)
Definition:
vector_altivec.h:133
i32
signed int i32
Definition:
types.h:77
u8x16
u8x16
Definition:
vector_sse42.h:194
i16
signed short i16
Definition:
types.h:46
right
vslo right
Definition:
vector_altivec.h:75
hi
vmrglw vmrglh hi
Definition:
vector_altivec.h:99
i64x2
epu8_epi32 epu16_epi32 epu32_epi64 epi8_epi32 epi16_epi32 i64x2
Definition:
vector_sse42.h:648
u32x4_word_shift_right
#define u32x4_word_shift_right(a, n)
Definition:
vector_sse42.h:328
i32x4
i32x4
Definition:
vector_altivec.h:95
left
left
Definition:
vector_altivec.h:73
always_inline
#define always_inline
Definition:
rdma_mlx5dv.h:23
u16x8
_mm_packus_epi16 u16x8
Definition:
vector_sse42.h:196
u32
unsigned int u32
Definition:
types.h:88
u32x4
unsigned long long u32x4
Definition:
ixge.c:28
i16x8
vmrglw i16x8
Definition:
vector_altivec.h:97
lo
lo
Definition:
vector_altivec.h:95
rotate_left
static uword rotate_left(uword x, uword i)
Definition:
bitops.h:142
src
vppinfra
vector_altivec.h
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