FD.io VPP
v21.06-3-gbb25fbf28
Vector Packet Processing
perfmon_intel_skl.c
Go to the documentation of this file.
1
2
#include <
perfmon/perfmon_intel.h
>
3
4
static
perfmon_intel_pmc_cpu_model_t
cpu_model_table
[] = {
5
{0x4E, 0x00, 0},
6
{0x5E, 0x00, 0},
7
{0x8E, 0x00, 0},
8
{0x9E, 0x00, 0},
9
10
};
11
12
static
perfmon_intel_pmc_event_t
event_table
[] = {
13
{
14
.
event_code
= {0x00},
15
.umask = 0x01,
16
.event_name =
"inst_retired.any"
,
17
},
18
{
19
.event_code = {0x00},
20
.umask = 0x02,
21
.event_name =
"cpu_clk_unhalted.thread"
,
22
},
23
{
24
.event_code = {0x00},
25
.umask = 0x02,
26
.event_name =
"cpu_clk_unhalted.thread_any"
,
27
},
28
{
29
.event_code = {0x00},
30
.umask = 0x03,
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.event_name =
"cpu_clk_unhalted.ref_tsc"
,
32
},
33
{
34
.event_code = {0x03},
35
.umask = 0x02,
36
.event_name =
"ld_blocks.store_forward"
,
37
},
38
{
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.event_code = {0x03},
40
.umask = 0x08,
41
.event_name =
"ld_blocks.no_sr"
,
42
},
43
{
44
.event_code = {0x07},
45
.umask = 0x01,
46
.event_name =
"ld_blocks_partial.address_alias"
,
47
},
48
{
49
.event_code = {0x08},
50
.umask = 0x01,
51
.event_name =
"dtlb_load_misses.miss_causes_a_walk"
,
52
},
53
{
54
.event_code = {0x08},
55
.umask = 0x02,
56
.event_name =
"dtlb_load_misses.walk_completed_4k"
,
57
},
58
{
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.event_code = {0x08},
60
.umask = 0x04,
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.event_name =
"dtlb_load_misses.walk_completed_2m_4m"
,
62
},
63
{
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.event_code = {0x08},
65
.umask = 0x08,
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.event_name =
"dtlb_load_misses.walk_completed_1g"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x0E,
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.event_name =
"dtlb_load_misses.walk_completed"
,
72
},
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{
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.event_code = {0x08},
75
.umask = 0x10,
76
.event_name =
"dtlb_load_misses.walk_pending"
,
77
},
78
{
79
.event_code = {0x08},
80
.umask = 0x20,
81
.event_name =
"dtlb_load_misses.stlb_hit"
,
82
},
83
{
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.event_code = {0x0D},
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.umask = 0x01,
86
.event_name =
"int_misc.recovery_cycles"
,
87
},
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{
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.event_code = {0x0D},
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.umask = 0x01,
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.anyt = 1,
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.event_name =
"int_misc.recovery_cycles_any"
,
93
},
94
{
95
.event_code = {0x0D},
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.umask = 0x80,
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.event_name =
"int_misc.clear_resteer_cycles"
,
98
},
99
{
100
.event_code = {0x0E},
101
.umask = 0x01,
102
.event_name =
"uops_issued.any"
,
103
},
104
{
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.event_code = {0x0E},
106
.umask = 0x01,
107
.cmask = 1,
108
.inv = 1,
109
.event_name =
"uops_issued.stall_cycles"
,
110
},
111
{
112
.event_code = {0x0E},
113
.umask = 0x20,
114
.event_name =
"uops_issued.slow_lea"
,
115
},
116
{
117
.event_code = {0x14},
118
.umask = 0x01,
119
.event_name =
"arith.divider_active"
,
120
},
121
{
122
.event_code = {0x24},
123
.umask = 0x21,
124
.event_name =
"l2_rqsts.demand_data_rd_miss"
,
125
},
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{
127
.event_code = {0x24},
128
.umask = 0x22,
129
.event_name =
"l2_rqsts.rfo_miss"
,
130
},
131
{
132
.event_code = {0x24},
133
.umask = 0x24,
134
.event_name =
"l2_rqsts.code_rd_miss"
,
135
},
136
{
137
.event_code = {0x24},
138
.umask = 0x27,
139
.event_name =
"l2_rqsts.all_demand_miss"
,
140
},
141
{
142
.event_code = {0x24},
143
.umask = 0x38,
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.event_name =
"l2_rqsts.pf_miss"
,
145
},
146
{
147
.event_code = {0x24},
148
.umask = 0x3F,
149
.event_name =
"l2_rqsts.miss"
,
150
},
151
{
152
.event_code = {0x24},
153
.umask = 0xc1,
154
.event_name =
"l2_rqsts.demand_data_rd_hit"
,
155
},
156
{
157
.event_code = {0x24},
158
.umask = 0xc2,
159
.event_name =
"l2_rqsts.rfo_hit"
,
160
},
161
{
162
.event_code = {0x24},
163
.umask = 0xc4,
164
.event_name =
"l2_rqsts.code_rd_hit"
,
165
},
166
{
167
.event_code = {0x24},
168
.umask = 0xd8,
169
.event_name =
"l2_rqsts.pf_hit"
,
170
},
171
{
172
.event_code = {0x24},
173
.umask = 0xE1,
174
.event_name =
"l2_rqsts.all_demand_data_rd"
,
175
},
176
{
177
.event_code = {0x24},
178
.umask = 0xE2,
179
.event_name =
"l2_rqsts.all_rfo"
,
180
},
181
{
182
.event_code = {0x24},
183
.umask = 0xE4,
184
.event_name =
"l2_rqsts.all_code_rd"
,
185
},
186
{
187
.event_code = {0x24},
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.umask = 0xe7,
189
.event_name =
"l2_rqsts.all_demand_references"
,
190
},
191
{
192
.event_code = {0x24},
193
.umask = 0xF8,
194
.event_name =
"l2_rqsts.all_pf"
,
195
},
196
{
197
.event_code = {0x24},
198
.umask = 0xFF,
199
.event_name =
"l2_rqsts.references"
,
200
},
201
{
202
.event_code = {0x2E},
203
.umask = 0x41,
204
.event_name =
"longest_lat_cache.miss"
,
205
},
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{
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.event_code = {0x2E},
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.umask = 0x4F,
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.event_name =
"longest_lat_cache.reference"
,
210
},
211
{
212
.event_code = {0x32},
213
.umask = 0x01,
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.event_name =
"sw_prefetch_access.nta"
,
215
},
216
{
217
.event_code = {0x32},
218
.umask = 0x02,
219
.event_name =
"sw_prefetch_access.t0"
,
220
},
221
{
222
.event_code = {0x32},
223
.umask = 0x04,
224
.event_name =
"sw_prefetch_access.t1_t2"
,
225
},
226
{
227
.event_code = {0x32},
228
.umask = 0x08,
229
.event_name =
"sw_prefetch_access.prefetchw"
,
230
},
231
{
232
.event_code = {0x3C},
233
.umask = 0x00,
234
.event_name =
"cpu_clk_unhalted.thread_p"
,
235
},
236
{
237
.event_code = {0x3C},
238
.umask = 0x00,
239
.anyt = 1,
240
.event_name =
"cpu_clk_unhalted.thread_p_any"
,
241
},
242
{
243
.event_code = {0x3C},
244
.umask = 0x00,
245
.event_name =
"cpu_clk_unhalted.ring0_trans"
,
246
},
247
{
248
.event_code = {0x3C},
249
.umask = 0x01,
250
.event_name =
"cpu_clk_thread_unhalted.ref_xclk"
,
251
},
252
{
253
.event_code = {0x3C},
254
.umask = 0x01,
255
.anyt = 1,
256
.event_name =
"cpu_clk_thread_unhalted.ref_xclk_any"
,
257
},
258
{
259
.event_code = {0x3C},
260
.umask = 0x01,
261
.event_name =
"cpu_clk_unhalted.ref_xclk"
,
262
},
263
{
264
.event_code = {0x3C},
265
.umask = 0x01,
266
.event_name =
"cpu_clk_unhalted.ref_xclk_any"
,
267
},
268
{
269
.event_code = {0x3C},
270
.umask = 0x02,
271
.event_name =
"cpu_clk_thread_unhalted.one_thread_active"
,
272
},
273
{
274
.event_code = {0x48},
275
.umask = 0x01,
276
.cmask = 1,
277
.event_name =
"l1d_pend_miss.pending"
,
278
},
279
{
280
.event_code = {0x48},
281
.umask = 0x01,
282
.event_name =
"l1d_pend_miss.pending_cycles"
,
283
},
284
{
285
.event_code = {0x48},
286
.umask = 0x02,
287
.event_name =
"l1d_pend_miss.fb_full"
,
288
},
289
{
290
.event_code = {0x49},
291
.umask = 0x01,
292
.event_name =
"dtlb_store_misses.miss_causes_a_walk"
,
293
},
294
{
295
.event_code = {0x49},
296
.umask = 0x02,
297
.event_name =
"dtlb_store_misses.walk_completed_4k"
,
298
},
299
{
300
.event_code = {0x49},
301
.umask = 0x04,
302
.event_name =
"dtlb_store_misses.walk_completed_2m_4m"
,
303
},
304
{
305
.event_code = {0x49},
306
.umask = 0x08,
307
.event_name =
"dtlb_store_misses.walk_completed_1g"
,
308
},
309
{
310
.event_code = {0x49},
311
.umask = 0x0E,
312
.event_name =
"dtlb_store_misses.walk_completed"
,
313
},
314
{
315
.event_code = {0x49},
316
.umask = 0x10,
317
.cmask = 1,
318
.event_name =
"dtlb_store_misses.walk_active"
,
319
},
320
{
321
.event_code = {0x49},
322
.umask = 0x10,
323
.event_name =
"dtlb_store_misses.walk_pending"
,
324
},
325
{
326
.event_code = {0x49},
327
.umask = 0x20,
328
.event_name =
"dtlb_store_misses.stlb_hit"
,
329
},
330
{
331
.event_code = {0x4C},
332
.umask = 0x01,
333
.event_name =
"load_hit_pre.sw_pf"
,
334
},
335
{
336
.event_code = {0x4F},
337
.umask = 0x10,
338
.event_name =
"ept.walk_pending"
,
339
},
340
{
341
.event_code = {0x51},
342
.umask = 0x01,
343
.event_name =
"l1d.replacement"
,
344
},
345
{
346
.event_code = {0x54},
347
.umask = 0x01,
348
.event_name =
"tx_mem.abort_conflict"
,
349
},
350
{
351
.event_code = {0x54},
352
.umask = 0x02,
353
.event_name =
"tx_mem.abort_capacity"
,
354
},
355
{
356
.event_code = {0x54},
357
.umask = 0x04,
358
.event_name =
"tx_mem.abort_hle_store_to_elided_lock"
,
359
},
360
{
361
.event_code = {0x54},
362
.umask = 0x08,
363
.event_name =
"tx_mem.abort_hle_elision_buffer_not_empty"
,
364
},
365
{
366
.event_code = {0x54},
367
.umask = 0x10,
368
.event_name =
"tx_mem.abort_hle_elision_buffer_mismatch"
,
369
},
370
{
371
.event_code = {0x54},
372
.umask = 0x20,
373
.event_name =
"tx_mem.abort_hle_elision_buffer_unsupported_alignment"
,
374
},
375
{
376
.event_code = {0x54},
377
.umask = 0x40,
378
.event_name =
"tx_mem.hle_elision_buffer_full"
,
379
},
380
{
381
.event_code = {0x59},
382
.umask = 0x01,
383
.event_name =
"partial_rat_stalls.scoreboard"
,
384
},
385
{
386
.event_code = {0x5d},
387
.umask = 0x01,
388
.event_name =
"tx_exec.misc1"
,
389
},
390
{
391
.event_code = {0x5d},
392
.umask = 0x02,
393
.event_name =
"tx_exec.misc2"
,
394
},
395
{
396
.event_code = {0x5d},
397
.umask = 0x04,
398
.event_name =
"tx_exec.misc3"
,
399
},
400
{
401
.event_code = {0x5d},
402
.umask = 0x08,
403
.event_name =
"tx_exec.misc4"
,
404
},
405
{
406
.event_code = {0x5d},
407
.umask = 0x10,
408
.event_name =
"tx_exec.misc5"
,
409
},
410
{
411
.event_code = {0x5E},
412
.umask = 0x01,
413
.event_name =
"rs_events.empty_cycles"
,
414
},
415
{
416
.event_code = {0x5E},
417
.umask = 0x01,
418
.cmask = 1,
419
.inv = 1,
420
.event_name =
"rs_events.empty_end"
,
421
},
422
{
423
.event_code = {0x60},
424
.umask = 0x01,
425
.event_name =
"offcore_requests_outstanding.demand_data_rd"
,
426
},
427
{
428
.event_code = {0x60},
429
.umask = 0x01,
430
.cmask = 1,
431
.event_name =
"offcore_requests_outstanding.cycles_with_demand_data_rd"
,
432
},
433
{
434
.event_code = {0x60},
435
.umask = 0x02,
436
.event_name =
"offcore_requests_outstanding.demand_code_rd"
,
437
},
438
{
439
.event_code = {0x60},
440
.umask = 0x02,
441
.cmask = 1,
442
.event_name =
"offcore_requests_outstanding.cycles_with_demand_code_rd"
,
443
},
444
{
445
.event_code = {0x60},
446
.umask = 0x04,
447
.event_name =
"offcore_requests_outstanding.demand_rfo"
,
448
},
449
{
450
.event_code = {0x60},
451
.umask = 0x04,
452
.cmask = 1,
453
.event_name =
"offcore_requests_outstanding.cycles_with_demand_rfo"
,
454
},
455
{
456
.event_code = {0x60},
457
.umask = 0x08,
458
.event_name =
"offcore_requests_outstanding.all_data_rd"
,
459
},
460
{
461
.event_code = {0x60},
462
.umask = 0x08,
463
.cmask = 1,
464
.event_name =
"offcore_requests_outstanding.cycles_with_data_rd"
,
465
},
466
{
467
.event_code = {0x60},
468
.umask = 0x10,
469
.event_name =
"offcore_requests_outstanding.l3_miss_demand_data_rd"
,
470
},
471
{
472
.event_code = {0x79},
473
.umask = 0x04,
474
.event_name =
"idq.mite_uops"
,
475
},
476
{
477
.event_code = {0x79},
478
.umask = 0x04,
479
.cmask = 1,
480
.event_name =
"idq.mite_cycles"
,
481
},
482
{
483
.event_code = {0x79},
484
.umask = 0x08,
485
.event_name =
"idq.dsb_uops"
,
486
},
487
{
488
.event_code = {0x79},
489
.umask = 0x08,
490
.cmask = 1,
491
.event_name =
"idq.dsb_cycles"
,
492
},
493
{
494
.event_code = {0x79},
495
.umask = 0x10,
496
.event_name =
"idq.ms_dsb_cycles"
,
497
},
498
{
499
.event_code = {0x79},
500
.umask = 0x18,
501
.cmask = 4,
502
.event_name =
"idq.all_dsb_cycles_4_uops"
,
503
},
504
{
505
.event_code = {0x79},
506
.umask = 0x18,
507
.cmask = 1,
508
.event_name =
"idq.all_dsb_cycles_any_uops"
,
509
},
510
{
511
.event_code = {0x79},
512
.umask = 0x20,
513
.event_name =
"idq.ms_mite_uops"
,
514
},
515
{
516
.event_code = {0x79},
517
.umask = 0x24,
518
.event_name =
"idq.all_mite_cycles_4_uops"
,
519
},
520
{
521
.event_code = {0x79},
522
.umask = 0x24,
523
.event_name =
"idq.all_mite_cycles_any_uops"
,
524
},
525
{
526
.event_code = {0x79},
527
.umask = 0x30,
528
.cmask = 1,
529
.event_name =
"idq.ms_cycles"
,
530
},
531
{
532
.event_code = {0x79},
533
.umask = 0x30,
534
.edge = 1,
535
.event_name =
"idq.ms_switches"
,
536
},
537
{
538
.event_code = {0x79},
539
.umask = 0x30,
540
.event_name =
"idq.ms_uops"
,
541
},
542
{
543
.event_code = {0x80},
544
.umask = 0x04,
545
.event_name =
"icache_16b.ifdata_stall"
,
546
},
547
{
548
.event_code = {0x83},
549
.umask = 0x01,
550
.event_name =
"icache_64b.iftag_hit"
,
551
},
552
{
553
.event_code = {0x83},
554
.umask = 0x02,
555
.event_name =
"icache_64b.iftag_miss"
,
556
},
557
{
558
.event_code = {0x83},
559
.umask = 0x04,
560
.event_name =
"icache_64b.iftag_stall"
,
561
},
562
{
563
.event_code = {0x85},
564
.umask = 0x01,
565
.event_name =
"itlb_misses.miss_causes_a_walk"
,
566
},
567
{
568
.event_code = {0x85},
569
.umask = 0x02,
570
.event_name =
"itlb_misses.walk_completed_4k"
,
571
},
572
{
573
.event_code = {0x85},
574
.umask = 0x04,
575
.event_name =
"itlb_misses.walk_completed_2m_4m"
,
576
},
577
{
578
.event_code = {0x85},
579
.umask = 0x08,
580
.event_name =
"itlb_misses.walk_completed_1g"
,
581
},
582
{
583
.event_code = {0x85},
584
.umask = 0x0E,
585
.event_name =
"itlb_misses.walk_completed"
,
586
},
587
{
588
.event_code = {0x85},
589
.umask = 0x10,
590
.event_name =
"itlb_misses.walk_pending"
,
591
},
592
{
593
.event_code = {0x85},
594
.umask = 0x10,
595
.event_name =
"itlb_misses.walk_active"
,
596
},
597
{
598
.event_code = {0x85},
599
.umask = 0x20,
600
.event_name =
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601
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602
{
603
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604
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605
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606
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607
{
608
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609
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610
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611
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612
{
613
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614
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615
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616
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617
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618
{
619
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620
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621
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622
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623
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624
{
625
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626
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627
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628
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629
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630
{
631
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632
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633
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634
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635
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636
{
637
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638
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639
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640
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641
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642
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643
{
644
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645
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646
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647
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648
{
649
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650
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651
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652
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653
{
654
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655
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656
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657
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658
{
659
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660
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661
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662
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663
{
664
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665
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666
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667
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668
{
669
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670
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671
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672
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673
{
674
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675
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676
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677
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678
{
679
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680
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681
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682
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683
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684
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685
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686
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687
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688
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689
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690
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691
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692
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693
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694
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695
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696
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697
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698
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699
{
700
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701
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702
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704
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705
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706
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707
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708
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709
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710
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711
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712
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713
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714
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715
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716
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717
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718
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719
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720
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721
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722
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723
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724
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725
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726
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727
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728
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729
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730
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732
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733
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734
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735
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736
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737
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738
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739
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740
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741
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742
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743
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744
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746
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748
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751
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754
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756
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759
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761
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762
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763
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764
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765
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766
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767
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768
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769
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770
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771
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772
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773
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774
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775
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776
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777
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778
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779
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781
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783
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784
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785
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786
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788
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789
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790
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791
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792
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793
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794
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795
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796
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797
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798
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799
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800
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801
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803
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804
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805
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806
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807
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808
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810
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811
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813
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814
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815
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816
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818
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820
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821
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823
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825
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826
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827
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828
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830
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831
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833
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835
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841
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844
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847
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849
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850
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851
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853
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855
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856
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857
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859
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862
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864
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866
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868
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870
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874
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876
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880
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882
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886
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888
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894
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895
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896
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897
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898
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900
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902
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903
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904
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905
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906
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907
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908
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909
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910
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911
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912
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913
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914
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915
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917
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918
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919
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920
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921
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922
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923
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924
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925
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927
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929
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930
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931
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932
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933
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934
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935
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936
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937
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938
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939
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940
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941
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943
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944
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945
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946
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948
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950
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951
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952
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953
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955
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957
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958
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959
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960
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961
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962
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963
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964
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965
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966
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967
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969
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970
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971
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972
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973
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974
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975
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977
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978
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979
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980
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981
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982
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983
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984
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985
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987
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988
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989
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990
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992
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993
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994
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995
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997
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999
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1000
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1002
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1004
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1005
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1006
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1007
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1008
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1009
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1010
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1012
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1013
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1014
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1015
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1016
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1017
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1018
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1019
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1020
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1021
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1022
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1023
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1024
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1025
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1027
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1028
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1029
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1030
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1031
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1032
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1033
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1034
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1035
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1036
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1037
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1038
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1039
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1040
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1042
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1043
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1044
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1045
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1047
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1048
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1049
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1050
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1052
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1053
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1054
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1055
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1057
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1058
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1059
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1060
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1062
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1063
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1065
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1067
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1070
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1072
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1073
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1075
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1077
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1079
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1080
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1082
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1083
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1085
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1086
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1087
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1088
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1090
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1092
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1093
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1095
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1100
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1102
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1105
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1107
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1110
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1112
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1115
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1117
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1120
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1121
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1122
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1124
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1125
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1127
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1128
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1129
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1130
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1132
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1133
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1134
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1135
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1137
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1140
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1141
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1142
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1143
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1144
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1146
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1147
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1148
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1149
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1150
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1151
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1152
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1153
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1154
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1155
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1156
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1157
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1158
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1159
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1160
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1161
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1162
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1163
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1164
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1165
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1166
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1167
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1168
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1169
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1170
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1171
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1172
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1173
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1174
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1175
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1176
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1177
{
1178
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1179
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1180
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1181
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1182
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1183
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1184
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1185
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1186
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1187
{
1188
.event_code = {0xD0},
1189
.umask = 0x81,
1190
.event_name =
"mem_inst_retired.all_loads"
,
1191
},
1192
{
1193
.event_code = {0xD0},
1194
.umask = 0x82,
1195
.event_name =
"mem_inst_retired.all_stores"
,
1196
},
1197
{
1198
.event_code = {0xD1},
1199
.umask = 0x01,
1200
.event_name =
"mem_load_retired.l1_hit"
,
1201
},
1202
{
1203
.event_code = {0xD1},
1204
.umask = 0x02,
1205
.event_name =
"mem_load_retired.l2_hit"
,
1206
},
1207
{
1208
.event_code = {0xD1},
1209
.umask = 0x04,
1210
.event_name =
"mem_load_retired.l3_hit"
,
1211
},
1212
{
1213
.event_code = {0xD1},
1214
.umask = 0x08,
1215
.event_name =
"mem_load_retired.l1_miss"
,
1216
},
1217
{
1218
.event_code = {0xD1},
1219
.umask = 0x10,
1220
.event_name =
"mem_load_retired.l2_miss"
,
1221
},
1222
{
1223
.event_code = {0xD1},
1224
.umask = 0x20,
1225
.event_name =
"mem_load_retired.l3_miss"
,
1226
},
1227
{
1228
.event_code = {0xD1},
1229
.umask = 0x40,
1230
.event_name =
"mem_load_retired.fb_hit"
,
1231
},
1232
{
1233
.event_code = {0xD2},
1234
.umask = 0x01,
1235
.event_name =
"mem_load_l3_hit_retired.xsnp_miss"
,
1236
},
1237
{
1238
.event_code = {0xD2},
1239
.umask = 0x02,
1240
.event_name =
"mem_load_l3_hit_retired.xsnp_hit"
,
1241
},
1242
{
1243
.event_code = {0xD2},
1244
.umask = 0x04,
1245
.event_name =
"mem_load_l3_hit_retired.xsnp_hitm"
,
1246
},
1247
{
1248
.event_code = {0xD2},
1249
.umask = 0x08,
1250
.event_name =
"mem_load_l3_hit_retired.xsnp_none"
,
1251
},
1252
{
1253
.event_code = {0xD4},
1254
.umask = 0x04,
1255
.event_name =
"mem_load_misc_retired.uc"
,
1256
},
1257
{
1258
.event_code = {0xE6},
1259
.umask = 0x01,
1260
.event_name =
"baclears.any"
,
1261
},
1262
{
1263
.event_code = {0xF0},
1264
.umask = 0x40,
1265
.event_name =
"l2_trans.l2_wb"
,
1266
},
1267
{
1268
.event_code = {0xF1},
1269
.umask = 0x1F,
1270
.event_name =
"l2_lines_in.all"
,
1271
},
1272
{
1273
.event_code = {0xF2},
1274
.umask = 0x01,
1275
.event_name =
"l2_lines_out.silent"
,
1276
},
1277
{
1278
.event_code = {0xF2},
1279
.umask = 0x02,
1280
.event_name =
"l2_lines_out.non_silent"
,
1281
},
1282
{
1283
.event_code = {0xF2},
1284
.umask = 0x04,
1285
.event_name =
"l2_lines_out.useless_pref"
,
1286
},
1287
{
1288
.event_code = {0xF2},
1289
.umask = 0x04,
1290
.event_name =
"l2_lines_out.useless_hwpf"
,
1291
},
1292
{
1293
.event_code = {0xF4},
1294
.umask = 0x10,
1295
.event_name =
"sq_misc.split_lock"
,
1296
},
1297
{
1298
.event_name = 0,
1299
},
1300
};
1301
1302
PERFMON_REGISTER_INTEL_PMC
(
cpu_model_table
,
event_table
);
1303
event_table
static perfmon_intel_pmc_event_t event_table[]
Definition:
perfmon_intel_skl.c:12
perfmon_intel_pmc_event_t::event_code
u8 event_code[2]
Definition:
perfmon_intel.h:26
perfmon_intel_pmc_event_t
Definition:
perfmon_intel.h:24
PERFMON_REGISTER_INTEL_PMC
PERFMON_REGISTER_INTEL_PMC(cpu_model_table, event_table)
perfmon_intel_pmc_cpu_model_t
Definition:
perfmon_intel.h:35
cpu_model_table
static perfmon_intel_pmc_cpu_model_t cpu_model_table[]
Definition:
perfmon_intel_skl.c:4
perfmon_intel.h
extras
deprecated
perfmon
perfmon_intel_skl.c
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