FD.io VPP
v21.06-3-gbb25fbf28
Vector Packet Processing
perfmon_intel_hsw.c
Go to the documentation of this file.
1
2
#include <
perfmon/perfmon_intel.h
>
3
4
static
perfmon_intel_pmc_cpu_model_t
cpu_model_table
[] = {
5
{0x3C, 0x00, 0},
6
{0x45, 0x00, 0},
7
{0x46, 0x00, 0},
8
9
};
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11
static
perfmon_intel_pmc_event_t
event_table
[] = {
12
{
13
.
event_code
= {0x00},
14
.umask = 0x01,
15
.event_name =
"inst_retired.any"
,
16
},
17
{
18
.event_code = {0x00},
19
.umask = 0x02,
20
.event_name =
"cpu_clk_unhalted.thread"
,
21
},
22
{
23
.event_code = {0x00},
24
.umask = 0x02,
25
.event_name =
"cpu_clk_unhalted.thread_any"
,
26
},
27
{
28
.event_code = {0x00},
29
.umask = 0x03,
30
.event_name =
"cpu_clk_unhalted.ref_tsc"
,
31
},
32
{
33
.event_code = {0x03},
34
.umask = 0x02,
35
.event_name =
"ld_blocks.store_forward"
,
36
},
37
{
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.event_code = {0x03},
39
.umask = 0x08,
40
.event_name =
"ld_blocks.no_sr"
,
41
},
42
{
43
.event_code = {0x05},
44
.umask = 0x01,
45
.event_name =
"misalign_mem_ref.loads"
,
46
},
47
{
48
.event_code = {0x05},
49
.umask = 0x02,
50
.event_name =
"misalign_mem_ref.stores"
,
51
},
52
{
53
.event_code = {0x07},
54
.umask = 0x01,
55
.event_name =
"ld_blocks_partial.address_alias"
,
56
},
57
{
58
.event_code = {0x08},
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.umask = 0x01,
60
.event_name =
"dtlb_load_misses.miss_causes_a_walk"
,
61
},
62
{
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.event_code = {0x08},
64
.umask = 0x02,
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.event_name =
"dtlb_load_misses.walk_completed_4k"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x04,
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.event_name =
"dtlb_load_misses.walk_completed_2m_4m"
,
71
},
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{
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.event_code = {0x08},
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.umask = 0x08,
75
.event_name =
"dtlb_load_misses.walk_completed_1g"
,
76
},
77
{
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.event_code = {0x08},
79
.umask = 0x0e,
80
.event_name =
"dtlb_load_misses.walk_completed"
,
81
},
82
{
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.event_code = {0x08},
84
.umask = 0x10,
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.event_name =
"dtlb_load_misses.walk_duration"
,
86
},
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{
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.event_code = {0x08},
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.umask = 0x20,
90
.event_name =
"dtlb_load_misses.stlb_hit_4k"
,
91
},
92
{
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.event_code = {0x08},
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.umask = 0x40,
95
.event_name =
"dtlb_load_misses.stlb_hit_2m"
,
96
},
97
{
98
.event_code = {0x08},
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.umask = 0x60,
100
.event_name =
"dtlb_load_misses.stlb_hit"
,
101
},
102
{
103
.event_code = {0x08},
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.umask = 0x80,
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.event_name =
"dtlb_load_misses.pde_cache_miss"
,
106
},
107
{
108
.event_code = {0x0D},
109
.umask = 0x03,
110
.event_name =
"int_misc.recovery_cycles"
,
111
},
112
{
113
.event_code = {0x0D},
114
.umask = 0x03,
115
.event_name =
"int_misc.recovery_cycles_any"
,
116
},
117
{
118
.event_code = {0x0E},
119
.umask = 0x01,
120
.event_name =
"uops_issued.any"
,
121
},
122
{
123
.event_code = {0x0E},
124
.umask = 0x01,
125
.event_name =
"uops_issued.stall_cycles"
,
126
},
127
{
128
.event_code = {0x0E},
129
.umask = 0x01,
130
.event_name =
"uops_issued.core_stall_cycles"
,
131
},
132
{
133
.event_code = {0x0E},
134
.umask = 0x10,
135
.event_name =
"uops_issued.flags_merge"
,
136
},
137
{
138
.event_code = {0x0E},
139
.umask = 0x20,
140
.event_name =
"uops_issued.slow_lea"
,
141
},
142
{
143
.event_code = {0x0E},
144
.umask = 0x40,
145
.event_name =
"uops_issued.single_mul"
,
146
},
147
{
148
.event_code = {0x14},
149
.umask = 0x02,
150
.event_name =
"arith.divider_uops"
,
151
},
152
{
153
.event_code = {0x24},
154
.umask = 0x21,
155
.event_name =
"l2_rqsts.demand_data_rd_miss"
,
156
},
157
{
158
.event_code = {0x24},
159
.umask = 0x22,
160
.event_name =
"l2_rqsts.rfo_miss"
,
161
},
162
{
163
.event_code = {0x24},
164
.umask = 0x24,
165
.event_name =
"l2_rqsts.code_rd_miss"
,
166
},
167
{
168
.event_code = {0x24},
169
.umask = 0x27,
170
.event_name =
"l2_rqsts.all_demand_miss"
,
171
},
172
{
173
.event_code = {0x24},
174
.umask = 0x30,
175
.event_name =
"l2_rqsts.l2_pf_miss"
,
176
},
177
{
178
.event_code = {0x24},
179
.umask = 0x3F,
180
.event_name =
"l2_rqsts.miss"
,
181
},
182
{
183
.event_code = {0x24},
184
.umask = 0xc1,
185
.event_name =
"l2_rqsts.demand_data_rd_hit"
,
186
},
187
{
188
.event_code = {0x24},
189
.umask = 0xc2,
190
.event_name =
"l2_rqsts.rfo_hit"
,
191
},
192
{
193
.event_code = {0x24},
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.umask = 0xc4,
195
.event_name =
"l2_rqsts.code_rd_hit"
,
196
},
197
{
198
.event_code = {0x24},
199
.umask = 0xd0,
200
.event_name =
"l2_rqsts.l2_pf_hit"
,
201
},
202
{
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.event_code = {0x24},
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.umask = 0xE1,
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.event_name =
"l2_rqsts.all_demand_data_rd"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xE2,
210
.event_name =
"l2_rqsts.all_rfo"
,
211
},
212
{
213
.event_code = {0x24},
214
.umask = 0xE4,
215
.event_name =
"l2_rqsts.all_code_rd"
,
216
},
217
{
218
.event_code = {0x24},
219
.umask = 0xe7,
220
.event_name =
"l2_rqsts.all_demand_references"
,
221
},
222
{
223
.event_code = {0x24},
224
.umask = 0xF8,
225
.event_name =
"l2_rqsts.all_pf"
,
226
},
227
{
228
.event_code = {0x24},
229
.umask = 0xFF,
230
.event_name =
"l2_rqsts.references"
,
231
},
232
{
233
.event_code = {0x27},
234
.umask = 0x50,
235
.event_name =
"l2_demand_rqsts.wb_hit"
,
236
},
237
{
238
.event_code = {0x2E},
239
.umask = 0x41,
240
.event_name =
"longest_lat_cache.miss"
,
241
},
242
{
243
.event_code = {0x2E},
244
.umask = 0x4F,
245
.event_name =
"longest_lat_cache.reference"
,
246
},
247
{
248
.event_code = {0x3C},
249
.umask = 0x00,
250
.event_name =
"cpu_clk_unhalted.thread_p"
,
251
},
252
{
253
.event_code = {0x3C},
254
.umask = 0x00,
255
.event_name =
"cpu_clk_unhalted.thread_p_any"
,
256
},
257
{
258
.event_code = {0x3C},
259
.umask = 0x01,
260
.event_name =
"cpu_clk_thread_unhalted.ref_xclk"
,
261
},
262
{
263
.event_code = {0x3C},
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.umask = 0x01,
265
.event_name =
"cpu_clk_thread_unhalted.ref_xclk_any"
,
266
},
267
{
268
.event_code = {0x3c},
269
.umask = 0x02,
270
.event_name =
"cpu_clk_thread_unhalted.one_thread_active"
,
271
},
272
{
273
.event_code = {0x48},
274
.umask = 0x01,
275
.event_name =
"l1d_pend_miss.pending"
,
276
},
277
{
278
.event_code = {0x48},
279
.umask = 0x01,
280
.event_name =
"l1d_pend_miss.pending_cycles"
,
281
},
282
{
283
.event_code = {0x48},
284
.umask = 0x02,
285
.event_name =
"l1d_pend_miss.request_fb_full"
,
286
},
287
{
288
.event_code = {0x49},
289
.umask = 0x01,
290
.event_name =
"dtlb_store_misses.miss_causes_a_walk"
,
291
},
292
{
293
.event_code = {0x49},
294
.umask = 0x02,
295
.event_name =
"dtlb_store_misses.walk_completed_4k"
,
296
},
297
{
298
.event_code = {0x49},
299
.umask = 0x04,
300
.event_name =
"dtlb_store_misses.walk_completed_2m_4m"
,
301
},
302
{
303
.event_code = {0x49},
304
.umask = 0x08,
305
.event_name =
"dtlb_store_misses.walk_completed_1g"
,
306
},
307
{
308
.event_code = {0x49},
309
.umask = 0x0e,
310
.event_name =
"dtlb_store_misses.walk_completed"
,
311
},
312
{
313
.event_code = {0x49},
314
.umask = 0x10,
315
.event_name =
"dtlb_store_misses.walk_duration"
,
316
},
317
{
318
.event_code = {0x49},
319
.umask = 0x20,
320
.event_name =
"dtlb_store_misses.stlb_hit_4k"
,
321
},
322
{
323
.event_code = {0x49},
324
.umask = 0x40,
325
.event_name =
"dtlb_store_misses.stlb_hit_2m"
,
326
},
327
{
328
.event_code = {0x49},
329
.umask = 0x60,
330
.event_name =
"dtlb_store_misses.stlb_hit"
,
331
},
332
{
333
.event_code = {0x49},
334
.umask = 0x80,
335
.event_name =
"dtlb_store_misses.pde_cache_miss"
,
336
},
337
{
338
.event_code = {0x4c},
339
.umask = 0x01,
340
.event_name =
"load_hit_pre.sw_pf"
,
341
},
342
{
343
.event_code = {0x4c},
344
.umask = 0x02,
345
.event_name =
"load_hit_pre.hw_pf"
,
346
},
347
{
348
.event_code = {0x4f},
349
.umask = 0x10,
350
.event_name =
"ept.walk_cycles"
,
351
},
352
{
353
.event_code = {0x51},
354
.umask = 0x01,
355
.event_name =
"l1d.replacement"
,
356
},
357
{
358
.event_code = {0x54},
359
.umask = 0x01,
360
.event_name =
"tx_mem.abort_conflict"
,
361
},
362
{
363
.event_code = {0x54},
364
.umask = 0x02,
365
.event_name =
"tx_mem.abort_capacity_write"
,
366
},
367
{
368
.event_code = {0x54},
369
.umask = 0x04,
370
.event_name =
"tx_mem.abort_hle_store_to_elided_lock"
,
371
},
372
{
373
.event_code = {0x54},
374
.umask = 0x08,
375
.event_name =
"tx_mem.abort_hle_elision_buffer_not_empty"
,
376
},
377
{
378
.event_code = {0x54},
379
.umask = 0x10,
380
.event_name =
"tx_mem.abort_hle_elision_buffer_mismatch"
,
381
},
382
{
383
.event_code = {0x54},
384
.umask = 0x20,
385
.event_name =
"tx_mem.abort_hle_elision_buffer_unsupported_alignment"
,
386
},
387
{
388
.event_code = {0x54},
389
.umask = 0x40,
390
.event_name =
"tx_mem.hle_elision_buffer_full"
,
391
},
392
{
393
.event_code = {0x58},
394
.umask = 0x01,
395
.event_name =
"move_elimination.int_eliminated"
,
396
},
397
{
398
.event_code = {0x58},
399
.umask = 0x02,
400
.event_name =
"move_elimination.simd_eliminated"
,
401
},
402
{
403
.event_code = {0x58},
404
.umask = 0x04,
405
.event_name =
"move_elimination.int_not_eliminated"
,
406
},
407
{
408
.event_code = {0x58},
409
.umask = 0x08,
410
.event_name =
"move_elimination.simd_not_eliminated"
,
411
},
412
{
413
.event_code = {0x5C},
414
.umask = 0x01,
415
.event_name =
"cpl_cycles.ring0"
,
416
},
417
{
418
.event_code = {0x5C},
419
.umask = 0x01,
420
.event_name =
"cpl_cycles.ring0_trans"
,
421
},
422
{
423
.event_code = {0x5C},
424
.umask = 0x02,
425
.event_name =
"cpl_cycles.ring123"
,
426
},
427
{
428
.event_code = {0x5d},
429
.umask = 0x01,
430
.event_name =
"tx_exec.misc1"
,
431
},
432
{
433
.event_code = {0x5d},
434
.umask = 0x02,
435
.event_name =
"tx_exec.misc2"
,
436
},
437
{
438
.event_code = {0x5d},
439
.umask = 0x04,
440
.event_name =
"tx_exec.misc3"
,
441
},
442
{
443
.event_code = {0x5d},
444
.umask = 0x08,
445
.event_name =
"tx_exec.misc4"
,
446
},
447
{
448
.event_code = {0x5d},
449
.umask = 0x10,
450
.event_name =
"tx_exec.misc5"
,
451
},
452
{
453
.event_code = {0x5E},
454
.umask = 0x01,
455
.event_name =
"rs_events.empty_cycles"
,
456
},
457
{
458
.event_code = {0x5E},
459
.umask = 0x01,
460
.event_name =
"rs_events.empty_end"
,
461
},
462
{
463
.event_code = {0x60},
464
.umask = 0x01,
465
.event_name =
"offcore_requests_outstanding.demand_data_rd"
,
466
},
467
{
468
.event_code = {0x60},
469
.umask = 0x01,
470
.event_name =
"offcore_requests_outstanding.cycles_with_demand_data_rd"
,
471
},
472
{
473
.event_code = {0x60},
474
.umask = 0x02,
475
.event_name =
"offcore_requests_outstanding.demand_code_rd"
,
476
},
477
{
478
.event_code = {0x60},
479
.umask = 0x04,
480
.event_name =
"offcore_requests_outstanding.demand_rfo"
,
481
},
482
{
483
.event_code = {0x60},
484
.umask = 0x04,
485
.event_name =
"offcore_requests_outstanding.cycles_with_demand_rfo"
,
486
},
487
{
488
.event_code = {0x60},
489
.umask = 0x08,
490
.event_name =
"offcore_requests_outstanding.all_data_rd"
,
491
},
492
{
493
.event_code = {0x60},
494
.umask = 0x08,
495
.event_name =
"offcore_requests_outstanding.cycles_with_data_rd"
,
496
},
497
{
498
.event_code = {0x63},
499
.umask = 0x01,
500
.event_name =
"lock_cycles.split_lock_uc_lock_duration"
,
501
},
502
{
503
.event_code = {0x63},
504
.umask = 0x02,
505
.event_name =
"lock_cycles.cache_lock_duration"
,
506
},
507
{
508
.event_code = {0x79},
509
.umask = 0x02,
510
.event_name =
"idq.empty"
,
511
},
512
{
513
.event_code = {0x79},
514
.umask = 0x04,
515
.event_name =
"idq.mite_uops"
,
516
},
517
{
518
.event_code = {0x79},
519
.umask = 0x04,
520
.event_name =
"idq.mite_cycles"
,
521
},
522
{
523
.event_code = {0x79},
524
.umask = 0x08,
525
.event_name =
"idq.dsb_uops"
,
526
},
527
{
528
.event_code = {0x79},
529
.umask = 0x08,
530
.event_name =
"idq.dsb_cycles"
,
531
},
532
{
533
.event_code = {0x79},
534
.umask = 0x10,
535
.event_name =
"idq.ms_dsb_uops"
,
536
},
537
{
538
.event_code = {0x79},
539
.umask = 0x10,
540
.event_name =
"idq.ms_dsb_cycles"
,
541
},
542
{
543
.event_code = {0x79},
544
.umask = 0x10,
545
.event_name =
"idq.ms_dsb_occur"
,
546
},
547
{
548
.event_code = {0x79},
549
.umask = 0x18,
550
.event_name =
"idq.all_dsb_cycles_4_uops"
,
551
},
552
{
553
.event_code = {0x79},
554
.umask = 0x18,
555
.event_name =
"idq.all_dsb_cycles_any_uops"
,
556
},
557
{
558
.event_code = {0x79},
559
.umask = 0x20,
560
.event_name =
"idq.ms_mite_uops"
,
561
},
562
{
563
.event_code = {0x79},
564
.umask = 0x24,
565
.event_name =
"idq.all_mite_cycles_4_uops"
,
566
},
567
{
568
.event_code = {0x79},
569
.umask = 0x24,
570
.event_name =
"idq.all_mite_cycles_any_uops"
,
571
},
572
{
573
.event_code = {0x79},
574
.umask = 0x30,
575
.event_name =
"idq.ms_uops"
,
576
},
577
{
578
.event_code = {0x79},
579
.umask = 0x30,
580
.event_name =
"idq.ms_cycles"
,
581
},
582
{
583
.event_code = {0x79},
584
.umask = 0x30,
585
.event_name =
"idq.ms_switches"
,
586
},
587
{
588
.event_code = {0x79},
589
.umask = 0x3c,
590
.event_name =
"idq.mite_all_uops"
,
591
},
592
{
593
.event_code = {0x80},
594
.umask = 0x01,
595
.event_name =
"icache.hit"
,
596
},
597
{
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"other_assists.sse_to_avx"
,
1171
},
1172
{
1173
.event_code = {0xC1},
1174
.umask = 0x40,
1175
.event_name =
"other_assists.any_wb_assist"
,
1176
},
1177
{
1178
.event_code = {0xC2},
1179
.umask = 0x01,
1180
.event_name =
"uops_retired.all"
,
1181
},
1182
{
1183
.event_code = {0xC2},
1184
.umask = 0x01,
1185
.event_name =
"uops_retired.stall_cycles"
,
1186
},
1187
{
1188
.event_code = {0xC2},
1189
.umask = 0x01,
1190
.event_name =
"uops_retired.total_cycles"
,
1191
},
1192
{
1193
.event_code = {0xC2},
1194
.umask = 0x01,
1195
.event_name =
"uops_retired.core_stall_cycles"
,
1196
},
1197
{
1198
.event_code = {0xC2},
1199
.umask = 0x02,
1200
.event_name =
"uops_retired.retire_slots"
,
1201
},
1202
{
1203
.event_code = {0xC3},
1204
.umask = 0x01,
1205
.event_name =
"machine_clears.cycles"
,
1206
},
1207
{
1208
.event_code = {0xC3},
1209
.umask = 0x01,
1210
.event_name =
"machine_clears.count"
,
1211
},
1212
{
1213
.event_code = {0xC3},
1214
.umask = 0x02,
1215
.event_name =
"machine_clears.memory_ordering"
,
1216
},
1217
{
1218
.event_code = {0xC3},
1219
.umask = 0x04,
1220
.event_name =
"machine_clears.smc"
,
1221
},
1222
{
1223
.event_code = {0xC3},
1224
.umask = 0x20,
1225
.event_name =
"machine_clears.maskmov"
,
1226
},
1227
{
1228
.event_code = {0xC4},
1229
.umask = 0x00,
1230
.event_name =
"br_inst_retired.all_branches"
,
1231
},
1232
{
1233
.event_code = {0xC4},
1234
.umask = 0x01,
1235
.event_name =
"br_inst_retired.conditional"
,
1236
},
1237
{
1238
.event_code = {0xC4},
1239
.umask = 0x02,
1240
.event_name =
"br_inst_retired.near_call"
,
1241
},
1242
{
1243
.event_code = {0xC4},
1244
.umask = 0x02,
1245
.event_name =
"br_inst_retired.near_call_r3"
,
1246
},
1247
{
1248
.event_code = {0xC4},
1249
.umask = 0x04,
1250
.event_name =
"br_inst_retired.all_branches_pebs"
,
1251
},
1252
{
1253
.event_code = {0xC4},
1254
.umask = 0x08,
1255
.event_name =
"br_inst_retired.near_return"
,
1256
},
1257
{
1258
.event_code = {0xC4},
1259
.umask = 0x10,
1260
.event_name =
"br_inst_retired.not_taken"
,
1261
},
1262
{
1263
.event_code = {0xC4},
1264
.umask = 0x20,
1265
.event_name =
"br_inst_retired.near_taken"
,
1266
},
1267
{
1268
.event_code = {0xC4},
1269
.umask = 0x40,
1270
.event_name =
"br_inst_retired.far_branch"
,
1271
},
1272
{
1273
.event_code = {0xC5},
1274
.umask = 0x00,
1275
.event_name =
"br_misp_retired.all_branches"
,
1276
},
1277
{
1278
.event_code = {0xC5},
1279
.umask = 0x01,
1280
.event_name =
"br_misp_retired.conditional"
,
1281
},
1282
{
1283
.event_code = {0xC5},
1284
.umask = 0x04,
1285
.event_name =
"br_misp_retired.all_branches_pebs"
,
1286
},
1287
{
1288
.event_code = {0xC5},
1289
.umask = 0x20,
1290
.event_name =
"br_misp_retired.near_taken"
,
1291
},
1292
{
1293
.event_code = {0xC6},
1294
.umask = 0x07,
1295
.event_name =
"avx_insts.all"
,
1296
},
1297
{
1298
.event_code = {0xC8},
1299
.umask = 0x01,
1300
.event_name =
"hle_retired.start"
,
1301
},
1302
{
1303
.event_code = {0xc8},
1304
.umask = 0x02,
1305
.event_name =
"hle_retired.commit"
,
1306
},
1307
{
1308
.event_code = {0xc8},
1309
.umask = 0x04,
1310
.event_name =
"hle_retired.aborted"
,
1311
},
1312
{
1313
.event_code = {0xc8},
1314
.umask = 0x08,
1315
.event_name =
"hle_retired.aborted_misc1"
,
1316
},
1317
{
1318
.event_code = {0xc8},
1319
.umask = 0x10,
1320
.event_name =
"hle_retired.aborted_misc2"
,
1321
},
1322
{
1323
.event_code = {0xc8},
1324
.umask = 0x20,
1325
.event_name =
"hle_retired.aborted_misc3"
,
1326
},
1327
{
1328
.event_code = {0xc8},
1329
.umask = 0x40,
1330
.event_name =
"hle_retired.aborted_misc4"
,
1331
},
1332
{
1333
.event_code = {0xc8},
1334
.umask = 0x80,
1335
.event_name =
"hle_retired.aborted_misc5"
,
1336
},
1337
{
1338
.event_code = {0xC9},
1339
.umask = 0x01,
1340
.event_name =
"rtm_retired.start"
,
1341
},
1342
{
1343
.event_code = {0xc9},
1344
.umask = 0x02,
1345
.event_name =
"rtm_retired.commit"
,
1346
},
1347
{
1348
.event_code = {0xc9},
1349
.umask = 0x04,
1350
.event_name =
"rtm_retired.aborted"
,
1351
},
1352
{
1353
.event_code = {0xc9},
1354
.umask = 0x08,
1355
.event_name =
"rtm_retired.aborted_misc1"
,
1356
},
1357
{
1358
.event_code = {0xc9},
1359
.umask = 0x10,
1360
.event_name =
"rtm_retired.aborted_misc2"
,
1361
},
1362
{
1363
.event_code = {0xc9},
1364
.umask = 0x20,
1365
.event_name =
"rtm_retired.aborted_misc3"
,
1366
},
1367
{
1368
.event_code = {0xc9},
1369
.umask = 0x40,
1370
.event_name =
"rtm_retired.aborted_misc4"
,
1371
},
1372
{
1373
.event_code = {0xc9},
1374
.umask = 0x80,
1375
.event_name =
"rtm_retired.aborted_misc5"
,
1376
},
1377
{
1378
.event_code = {0xCA},
1379
.umask = 0x02,
1380
.event_name =
"fp_assist.x87_output"
,
1381
},
1382
{
1383
.event_code = {0xCA},
1384
.umask = 0x04,
1385
.event_name =
"fp_assist.x87_input"
,
1386
},
1387
{
1388
.event_code = {0xCA},
1389
.umask = 0x08,
1390
.event_name =
"fp_assist.simd_output"
,
1391
},
1392
{
1393
.event_code = {0xCA},
1394
.umask = 0x10,
1395
.event_name =
"fp_assist.simd_input"
,
1396
},
1397
{
1398
.event_code = {0xCA},
1399
.umask = 0x1E,
1400
.event_name =
"fp_assist.any"
,
1401
},
1402
{
1403
.event_code = {0xCC},
1404
.umask = 0x20,
1405
.event_name =
"rob_misc_events.lbr_inserts"
,
1406
},
1407
{
1408
.event_code = {0xD0},
1409
.umask = 0x11,
1410
.event_name =
"mem_uops_retired.stlb_miss_loads"
,
1411
},
1412
{
1413
.event_code = {0xD0},
1414
.umask = 0x12,
1415
.event_name =
"mem_uops_retired.stlb_miss_stores"
,
1416
},
1417
{
1418
.event_code = {0xD0},
1419
.umask = 0x21,
1420
.event_name =
"mem_uops_retired.lock_loads"
,
1421
},
1422
{
1423
.event_code = {0xD0},
1424
.umask = 0x41,
1425
.event_name =
"mem_uops_retired.split_loads"
,
1426
},
1427
{
1428
.event_code = {0xD0},
1429
.umask = 0x42,
1430
.event_name =
"mem_uops_retired.split_stores"
,
1431
},
1432
{
1433
.event_code = {0xD0},
1434
.umask = 0x81,
1435
.event_name =
"mem_uops_retired.all_loads"
,
1436
},
1437
{
1438
.event_code = {0xD0},
1439
.umask = 0x82,
1440
.event_name =
"mem_uops_retired.all_stores"
,
1441
},
1442
{
1443
.event_code = {0xD1},
1444
.umask = 0x01,
1445
.event_name =
"mem_load_uops_retired.l1_hit"
,
1446
},
1447
{
1448
.event_code = {0xD1},
1449
.umask = 0x02,
1450
.event_name =
"mem_load_uops_retired.l2_hit"
,
1451
},
1452
{
1453
.event_code = {0xD1},
1454
.umask = 0x04,
1455
.event_name =
"mem_load_uops_retired.l3_hit"
,
1456
},
1457
{
1458
.event_code = {0xD1},
1459
.umask = 0x08,
1460
.event_name =
"mem_load_uops_retired.l1_miss"
,
1461
},
1462
{
1463
.event_code = {0xD1},
1464
.umask = 0x10,
1465
.event_name =
"mem_load_uops_retired.l2_miss"
,
1466
},
1467
{
1468
.event_code = {0xD1},
1469
.umask = 0x20,
1470
.event_name =
"mem_load_uops_retired.l3_miss"
,
1471
},
1472
{
1473
.event_code = {0xD1},
1474
.umask = 0x40,
1475
.event_name =
"mem_load_uops_retired.hit_lfb"
,
1476
},
1477
{
1478
.event_code = {0xD2},
1479
.umask = 0x01,
1480
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_miss"
,
1481
},
1482
{
1483
.event_code = {0xD2},
1484
.umask = 0x02,
1485
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_hit"
,
1486
},
1487
{
1488
.event_code = {0xD2},
1489
.umask = 0x04,
1490
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_hitm"
,
1491
},
1492
{
1493
.event_code = {0xD2},
1494
.umask = 0x08,
1495
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_none"
,
1496
},
1497
{
1498
.event_code = {0xD3},
1499
.umask = 0x01,
1500
.event_name =
"mem_load_uops_l3_miss_retired.local_dram"
,
1501
},
1502
{
1503
.event_code = {0xe6},
1504
.umask = 0x1f,
1505
.event_name =
"baclears.any"
,
1506
},
1507
{
1508
.event_code = {0xf0},
1509
.umask = 0x01,
1510
.event_name =
"l2_trans.demand_data_rd"
,
1511
},
1512
{
1513
.event_code = {0xf0},
1514
.umask = 0x02,
1515
.event_name =
"l2_trans.rfo"
,
1516
},
1517
{
1518
.event_code = {0xf0},
1519
.umask = 0x04,
1520
.event_name =
"l2_trans.code_rd"
,
1521
},
1522
{
1523
.event_code = {0xf0},
1524
.umask = 0x08,
1525
.event_name =
"l2_trans.all_pf"
,
1526
},
1527
{
1528
.event_code = {0xf0},
1529
.umask = 0x10,
1530
.event_name =
"l2_trans.l1d_wb"
,
1531
},
1532
{
1533
.event_code = {0xf0},
1534
.umask = 0x20,
1535
.event_name =
"l2_trans.l2_fill"
,
1536
},
1537
{
1538
.event_code = {0xf0},
1539
.umask = 0x40,
1540
.event_name =
"l2_trans.l2_wb"
,
1541
},
1542
{
1543
.event_code = {0xf0},
1544
.umask = 0x80,
1545
.event_name =
"l2_trans.all_requests"
,
1546
},
1547
{
1548
.event_code = {0xF1},
1549
.umask = 0x01,
1550
.event_name =
"l2_lines_in.i"
,
1551
},
1552
{
1553
.event_code = {0xF1},
1554
.umask = 0x02,
1555
.event_name =
"l2_lines_in.s"
,
1556
},
1557
{
1558
.event_code = {0xF1},
1559
.umask = 0x04,
1560
.event_name =
"l2_lines_in.e"
,
1561
},
1562
{
1563
.event_code = {0xF1},
1564
.umask = 0x07,
1565
.event_name =
"l2_lines_in.all"
,
1566
},
1567
{
1568
.event_code = {0xF2},
1569
.umask = 0x05,
1570
.event_name =
"l2_lines_out.demand_clean"
,
1571
},
1572
{
1573
.event_code = {0xF2},
1574
.umask = 0x06,
1575
.event_name =
"l2_lines_out.demand_dirty"
,
1576
},
1577
{
1578
.event_code = {0xf4},
1579
.umask = 0x10,
1580
.event_name =
"sq_misc.split_lock"
,
1581
},
1582
{
1583
.event_name = 0,
1584
},
1585
};
1586
1587
PERFMON_REGISTER_INTEL_PMC
(
cpu_model_table
,
event_table
);
1588
perfmon_intel_pmc_event_t::event_code
u8 event_code[2]
Definition:
perfmon_intel.h:26
perfmon_intel_pmc_event_t
Definition:
perfmon_intel.h:24
PERFMON_REGISTER_INTEL_PMC
PERFMON_REGISTER_INTEL_PMC(cpu_model_table, event_table)
perfmon_intel_pmc_cpu_model_t
Definition:
perfmon_intel.h:35
cpu_model_table
static perfmon_intel_pmc_cpu_model_t cpu_model_table[]
Definition:
perfmon_intel_hsw.c:4
event_table
static perfmon_intel_pmc_event_t event_table[]
Definition:
perfmon_intel_hsw.c:11
perfmon_intel.h
extras
deprecated
perfmon
perfmon_intel_hsw.c
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