FD.io VPP  v21.06-3-gbb25fbf28
Vector Packet Processing
ixge.h
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1 /*
2  * Copyright (c) 2016 Cisco and/or its affiliates.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at:
6  *
7  * http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef included_ixge_h
17 #define included_ixge_h
18 
19 #include <vnet/vnet.h>
20 #include <vlib/pci/pci.h>
21 #include <vlib/i2c.h>
22 #include <vnet/ethernet/sfp.h>
23 #include <vnet/ip/ip4_packet.h>
24 #include <vnet/ip/ip6_packet.h>
25 
26 typedef volatile struct
27 {
28  /* [31:7] 128 byte aligned. */
29  u32 descriptor_address[2];
31 
32  /* [5] rx/tx descriptor dca enable
33  [6] rx packet head dca enable
34  [7] rx packet tail dca enable
35  [9] rx/tx descriptor relaxed order
36  [11] rx/tx descriptor write back relaxed order
37  [13] rx/tx data write/read relaxed order
38  [15] rx head data write relaxed order
39  [31:24] apic id for cpu's cache. */
41 
43 
44  /* [4:0] tail buffer size (in 1k byte units)
45  [13:8] head buffer size (in 64 byte units)
46  [24:22] lo free descriptors threshold (units of 64 descriptors)
47  [27:25] descriptor type 0 = legacy, 1 = advanced one buffer (e.g. tail),
48  2 = advanced header splitting (head + tail), 5 = advanced header
49  splitting (head only).
50  [28] drop if no descriptors available. */
52 
54  CLIB_PAD_FROM_TO (0x1c, 0x28);
55 
56  /* [7:0] rx/tx prefetch threshold
57  [15:8] rx/tx host threshold
58  [24:16] rx/tx write back threshold
59  [25] rx/tx enable
60  [26] tx descriptor writeback flush
61  [30] rx strip vlan enable */
63 
65 
66  union
67  {
68  struct
69  {
70  /* packets bytes lo hi */
71  u32 stats[3];
72 
74  } rx;
75 
76  struct
77  {
78  u32 unused[2];
79 
80  /* [0] enables head write back. */
81  u32 head_index_write_back_address[2];
82  } tx;
83  };
85 
86 /* Only advanced descriptors are supported. */
87 typedef struct
88 {
92 
93 typedef struct
94 {
95  u32 status[3];
99 
100 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_LAYER2 (1 << (4 + 11))
101 /* Valid if not layer2. */
102 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4 (1 << (4 + 0))
103 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4_EXT (1 << (4 + 1))
104 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6 (1 << (4 + 2))
105 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6_EXT (1 << (4 + 3))
106 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_TCP (1 << (4 + 4))
107 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_UDP (1 << (4 + 5))
108 #define IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET(s) (((s) >> 21) & 0x3ff)
109 
110 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE (1 << (0 + 0))
111 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET (1 << (0 + 1))
112 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_VLAN (1 << (0 + 3))
113 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED (1 << (0 + 4))
114 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED (1 << (0 + 5))
115 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED (1 << (0 + 6))
116 #define IXGE_RX_DESCRIPTOR_STATUS2_NOT_UNICAST (1 << (0 + 7))
117 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_DOUBLE_VLAN (1 << (0 + 9))
118 #define IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR (1 << (0 + 10))
119 #define IXGE_RX_DESCRIPTOR_STATUS2_ETHERNET_ERROR (1 << (20 + 9))
120 #define IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR (1 << (20 + 10))
121 #define IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR (1 << (20 + 11))
122 
123 /* For layer2 packets stats0 bottom 3 bits give ether type index from filter. */
124 #define IXGE_RX_DESCRIPTOR_STATUS0_LAYER2_ETHERNET_TYPE(s) ((s) & 7)
125 
126 typedef struct
127 {
132 #define IXGE_TX_DESCRIPTOR_STATUS0_ADVANCED (3 << 4)
133 #define IXGE_TX_DESCRIPTOR_STATUS0_IS_ADVANCED (1 << (8 + 5))
134 #define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_REPORT_STATUS (8 + 3)
135 #define IXGE_TX_DESCRIPTOR_STATUS0_REPORT_STATUS (1 << IXGE_TX_DESCRIPTOR_STATUS0_LOG2_REPORT_STATUS)
136 #define IXGE_TX_DESCRIPTOR_STATUS0_INSERT_FCS (1 << (8 + 1))
137 #define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET (8 + 0)
138 #define IXGE_TX_DESCRIPTOR_STATUS0_IS_END_OF_PACKET (1 << IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET)
139 #define IXGE_TX_DESCRIPTOR_STATUS1_DONE (1 << 0)
140 #define IXGE_TX_DESCRIPTOR_STATUS1_CONTEXT(i) (/* valid */ (1 << 7) | ((i) << 4))
141 #define IXGE_TX_DESCRIPTOR_STATUS1_IPSEC_OFFLOAD (1 << (8 + 2))
142 #define IXGE_TX_DESCRIPTOR_STATUS1_INSERT_TCP_UDP_CHECKSUM (1 << (8 + 1))
143 #define IXGE_TX_DESCRIPTOR_STATUS1_INSERT_IP4_CHECKSUM (1 << (8 + 0))
144 #define IXGE_TX_DESCRIPTOR_STATUS0_N_BYTES_THIS_BUFFER(l) ((l) << 0)
145 #define IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET(l) ((l) << 14)
147 
148 typedef struct
149 {
150  struct
151  {
155  } ip, tcp;
157 
159 
160  /* Byte offset after UDP/TCP header. */
162 
164 } __attribute__ ((packed)) ixge_tx_context_descriptor_t;
165 
166 typedef union
167 {
173 
174 typedef volatile struct
175 {
176  /* [2] pcie master disable
177  [3] mac reset
178  [26] global device reset */
181  /* [3:2] device id (0 or 1 for dual port chips)
182  [7] link is up
183  [17:10] num vfs
184  [18] io active
185  [19] pcie master enable status */
187  CLIB_PAD_FROM_TO (0xc, 0x18);
188  /* [14] pf reset done
189  [17] relaxed ordering disable
190  [26] extended vlan enable
191  [28] driver loaded */
193  CLIB_PAD_FROM_TO (0x1c, 0x20);
194 
195  /* software definable pins.
196  sdp_data [7:0]
197  sdp_is_output [15:8]
198  sdp_is_native [23:16]
199  sdp_function [31:24].
200  */
202  CLIB_PAD_FROM_TO (0x24, 0x28);
203 
204  /* [0] i2c clock in
205  [1] i2c clock out
206  [2] i2c data in
207  [3] i2c data out */
209  CLIB_PAD_FROM_TO (0x2c, 0x4c);
211 
212  CLIB_PAD_FROM_TO (0x50, 0x200);
213 
215 
216  CLIB_PAD_FROM_TO (0x204, 0x600);
218  CLIB_PAD_FROM_TO (0x604, 0x700);
219 
220  struct
221  {
222  u32 vflr_events_clear[4];
223  u32 mailbox_interrupt_status[4];
224  u32 mailbox_interrupt_enable[4];
225  CLIB_PAD_FROM_TO (0x730, 0x800);
226  } pf_foo;
227 
228  struct
229  {
231  CLIB_PAD_FROM_TO (0x804, 0x808);
233  CLIB_PAD_FROM_TO (0x80c, 0x810);
235  CLIB_PAD_FROM_TO (0x814, 0x820);
236 
237  /* [11:3] minimum inter-interrupt interval
238  (2e-6 units; 20e-6 units for fast ethernet).
239  [15] low-latency interrupt moderation enable
240  [20:16] low-latency interrupt credit
241  [27:21] interval counter
242  [31] write disable for credit and counter (write only). */
243  u32 throttle0[24];
244 
246  CLIB_PAD_FROM_TO (0x884, 0x888);
248  CLIB_PAD_FROM_TO (0x88c, 0x890);
251  /* [3:0] spd 0-3 interrupt detection enable
252  [4] msi-x enable
253  [5] other clear disable (makes other bits in status not clear on read)
254  etc. */
255  u32 control;
256  CLIB_PAD_FROM_TO (0x89c, 0x900);
257 
258  /* Defines interrupt mapping for 128 rx + 128 tx queues.
259  64 x 4 8 bit entries.
260  For register [i]:
261  [5:0] bit in interrupt status for rx queue 2*i + 0
262  [7] valid bit
263  [13:8] bit for tx queue 2*i + 0
264  [15] valid bit
265  similar for rx 2*i + 1 and tx 2*i + 1. */
266  u32 queue_mapping[64];
267 
268  /* tcp timer [7:0] and other interrupts [15:8] */
270  CLIB_PAD_FROM_TO (0xa04, 0xa90);
271 
272  /* 64 interrupts determined by mappings. */
273  u32 status1_write_1_to_clear[4];
274  u32 enable1_write_1_to_set[4];
275  u32 enable1_write_1_to_clear[4];
276  CLIB_PAD_FROM_TO (0xac0, 0xad0);
277  u32 status1_enable_auto_clear[4];
278  CLIB_PAD_FROM_TO (0xae0, 0x1000);
279  } interrupt;
280 
281  ixge_dma_regs_t rx_dma0[64];
282 
283  CLIB_PAD_FROM_TO (0x2000, 0x2140);
284  u32 dcb_rx_packet_plane_t4_config[8];
285  u32 dcb_rx_packet_plane_t4_status[8];
286  CLIB_PAD_FROM_TO (0x2180, 0x2300);
287 
288  /* reg i defines mapping for 4 rx queues starting at 4*i + 0. */
289  u32 rx_queue_stats_mapping[32];
291 
292  CLIB_PAD_FROM_TO (0x2384, 0x2410);
293  u32 fc_user_descriptor_ptr[2];
295  CLIB_PAD_FROM_TO (0x241c, 0x2420);
297  CLIB_PAD_FROM_TO (0x2424, 0x2430);
299  CLIB_PAD_FROM_TO (0x2434, 0x2f00);
300 
303  CLIB_PAD_FROM_TO (0x2f08, 0x2f20);
305  CLIB_PAD_FROM_TO (0x2f24, 0x3000);
306 
307  /* 1 bit. */
309  CLIB_PAD_FROM_TO (0x3004, 0x3008);
310  /* [15:0] ether type (little endian)
311  [31:16] opcode (big endian) */
313  CLIB_PAD_FROM_TO (0x300c, 0x3020);
314  /* 3 bit traffic class for each of 8 priorities. */
316  CLIB_PAD_FROM_TO (0x3024, 0x3028);
318  CLIB_PAD_FROM_TO (0x302c, 0x3190);
320  CLIB_PAD_FROM_TO (0x3194, 0x3200);
321  u32 flow_control_tx_timers[4]; /* 2 timer values */
322  CLIB_PAD_FROM_TO (0x3210, 0x3220);
323  u32 flow_control_rx_threshold_lo[8];
324  CLIB_PAD_FROM_TO (0x3240, 0x3260);
325  u32 flow_control_rx_threshold_hi[8];
326  CLIB_PAD_FROM_TO (0x3280, 0x32a0);
328  CLIB_PAD_FROM_TO (0x32a4, 0x3c00);
329  /* For each of 8 traffic classes (units of bytes). */
330  u32 rx_packet_buffer_size[8];
331  CLIB_PAD_FROM_TO (0x3c20, 0x3d00);
333  CLIB_PAD_FROM_TO (0x3d04, 0x4200);
334 
335  struct
336  {
338  CLIB_PAD_FROM_TO (0x4204, 0x4208);
341  u32 pcs_debug[2];
346  CLIB_PAD_FROM_TO (0x4228, 0x4240);
347  } gige_mac;
348 
349  struct
350  {
351  /* [0] tx crc enable
352  [2] enable frames up to max frame size register [31:16]
353  [10] pad frames < 64 bytes if specified by user
354  [15] loopback enable
355  [16] mdc hi speed
356  [17] turn off mdc between mdio packets */
357  u32 control;
358 
359  /* [5] rx symbol error (all bits clear on read)
360  [6] rx illegal symbol
361  [7] rx idle error
362  [8] rx local fault
363  [9] rx remote fault */
365 
367  CLIB_PAD_FROM_TO (0x424c, 0x425c);
370  CLIB_PAD_FROM_TO (0x4264, 0x4268);
371 
372  /* [31:16] max frame size in bytes. */
374  CLIB_PAD_FROM_TO (0x426c, 0x4288);
375 
376  /* [0]
377  [2] pcs receive link up? (latch lo)
378  [7] local fault
379  [1]
380  [0] pcs 10g base r capable
381  [1] pcs 10g base x capable
382  [2] pcs 10g base w capable
383  [10] rx local fault
384  [11] tx local fault
385  [15:14] 2 => device present at this address (else not present) */
386  u32 xgxs_status[2];
387 
389 
390  /* [0] pass unrecognized flow control frames
391  [1] discard pause frames
392  [2] rx priority flow control enable (only in dcb mode)
393  [3] rx flow control enable. */
395 
396  /* [3:0] tx lanes change polarity
397  [7:4] rx lanes change polarity
398  [11:8] swizzle tx lanes
399  [15:12] swizzle rx lanes
400  4 x 2 bit tx lane swap
401  4 x 2 bit rx lane swap. */
403 
405 
406  /* [0] force link up
407  [1] autoneg ack2 bit to transmit
408  [6:2] autoneg selector field to transmit
409  [8:7] 10g pma/pmd type 0 => xaui, 1 kx4, 2 cx4
410  [9] 1g pma/pmd type 0 => sfi, 1 => kx/bx
411  [10] disable 10g on without main power
412  [11] restart autoneg on transition to dx power state
413  [12] restart autoneg
414  [15:13] link mode:
415  0 => 1g no autoneg
416  1 => 10g kx4 parallel link no autoneg
417  2 => 1g bx autoneg
418  3 => 10g sfi serdes
419  4 => kx4/kx/kr
420  5 => xgmii 1g/100m
421  6 => kx4/kx/kr 1g an
422  7 kx4/kx/kr sgmii.
423  [16] kr support
424  [17] fec requested
425  [18] fec ability
426  etc. */
428 
429  /* [0] signal detect 1g/100m
430  [1] fec signal detect
431  [2] 10g serial pcs fec block lock
432  [3] 10g serial high error rate
433  [4] 10g serial pcs block lock
434  [5] kx/kx4/kr autoneg next page received
435  [6] kx/kx4/kr backplane autoneg next page received
436  [7] link status clear to read
437  [11:8] 10g signal detect (4 lanes) (for serial just lane 0)
438  [12] 10g serial signal detect
439  [16:13] 10g parallel lane sync status
440  [17] 10g parallel align status
441  [18] 1g sync status
442  [19] kx/kx4/kr backplane autoneg is idle
443  [20] 1g autoneg enabled
444  [21] 1g pcs enabled for sgmii
445  [22] 10g xgxs enabled
446  [23] 10g serial fec enabled (forward error detection)
447  [24] 10g kr pcs enabled
448  [25] sgmii enabled
449  [27:26] mac link mode
450  0 => 1g
451  1 => 10g parallel
452  2 => 10g serial
453  3 => autoneg
454  [29:28] link speed
455  1 => 100m
456  2 => 1g
457  3 => 10g
458  [30] link is up
459  [31] kx/kx4/kr backplane autoneg completed successfully. */
460  u32 link_status;
461 
462  /* [17:16] pma/pmd for 10g serial
463  0 => kr, 2 => sfi
464  [18] disable dme pages */
466 
467  CLIB_PAD_FROM_TO (0x42ac, 0x42b0);
468  u32 link_partner_ability[2];
469  CLIB_PAD_FROM_TO (0x42b8, 0x42d0);
471  u32 link_partner_next_page[2];
472  CLIB_PAD_FROM_TO (0x42dc, 0x42e0);
475  u32 fec_status[2];
476  CLIB_PAD_FROM_TO (0x42f0, 0x4314);
478  CLIB_PAD_FROM_TO (0x4318, 0x4324);
480  CLIB_PAD_FROM_TO (0x4328, 0x4900);
481  } xge_mac;
482 
487  CLIB_PAD_FROM_TO (0x4910, 0x4950);
488 
489  /* For each TC in units of 1k bytes. */
490  u32 tx_packet_buffer_thresholds[8];
491  CLIB_PAD_FROM_TO (0x4970, 0x4980);
492  struct
493  {
496  u32 status;
498  } dcb_tx_rate_scheduler;
499  CLIB_PAD_FROM_TO (0x4990, 0x4a80);
501  CLIB_PAD_FROM_TO (0x4a84, 0x4a88);
502  u32 tx_dma_tcp_flags_control[2];
503  CLIB_PAD_FROM_TO (0x4a90, 0x4b00);
504  u32 pf_mailbox[64];
505  CLIB_PAD_FROM_TO (0x4c00, 0x5000);
506 
507  /* RX */
509  CLIB_PAD_FROM_TO (0x5004, 0x5008);
511  CLIB_PAD_FROM_TO (0x500c, 0x5010);
512  u32 management_vlan_tag[8];
513  u32 management_udp_tcp_ports[8];
514  CLIB_PAD_FROM_TO (0x5050, 0x5078);
515  /* little endian. */
517  CLIB_PAD_FROM_TO (0x507c, 0x5080);
518  /* [1] store/dma bad packets
519  [8] accept all multicast
520  [9] accept all unicast
521  [10] accept all broadcast. */
523  CLIB_PAD_FROM_TO (0x5084, 0x5088);
524  /* [15:0] vlan ethernet type (0x8100) little endian
525  [28] cfi bit expected
526  [29] drop packets with unexpected cfi bit
527  [30] vlan filter enable. */
529  CLIB_PAD_FROM_TO (0x508c, 0x5090);
530  /* [1:0] hi bit of ethernet address for 12 bit index into multicast table
531  0 => 47, 1 => 46, 2 => 45, 3 => 43.
532  [2] enable multicast filter
533  */
535  CLIB_PAD_FROM_TO (0x5094, 0x5100);
537  CLIB_PAD_FROM_TO (0x5104, 0x5108);
539  CLIB_PAD_FROM_TO (0x510c, 0x5110);
541  CLIB_PAD_FROM_TO (0x5114, 0x5120);
543  CLIB_PAD_FROM_TO (0x5124, 0x5128);
544  /* [15:0] ethernet type (little endian)
545  [18:16] matche pri in vlan tag
546  [19] priority match enable
547  [25:20] virtualization pool
548  [26] pool enable
549  [27] is fcoe
550  [30] ieee 1588 timestamp enable
551  [31] filter enable.
552  (See ethernet_type_queue_select.) */
553  u32 ethernet_type_queue_filter[8];
554  CLIB_PAD_FROM_TO (0x5148, 0x5160);
555  /* [7:0] l2 ethernet type and
556  [15:8] l2 ethernet type or */
557  u32 management_decision_filters1[8];
558  u32 vf_vm_tx_switch_loopback_enable[2];
560  CLIB_PAD_FROM_TO (0x518c, 0x5190);
561  u32 management_ethernet_type_filters[4];
565  CLIB_PAD_FROM_TO (0x51ac, 0x51b0);
567  CLIB_PAD_FROM_TO (0x51b4, 0x51d8);
569  CLIB_PAD_FROM_TO (0x51dc, 0x51e0);
570  u32 vf_rx_enable[2];
572  CLIB_PAD_FROM_TO (0x51ec, 0x5200);
573  /* 12 bits determined by multicast_control
574  lookup bits in this vector. */
575  u32 multicast_enable[128];
576 
577  /* [0] ethernet address [31:0]
578  [1] [15:0] ethernet address [47:32]
579  [31] valid bit.
580  Index 0 is read from eeprom after reset. */
581  u32 rx_ethernet_address0[16][2];
582 
583  CLIB_PAD_FROM_TO (0x5480, 0x5800);
585  CLIB_PAD_FROM_TO (0x5804, 0x5808);
587  CLIB_PAD_FROM_TO (0x580c, 0x5818);
589  CLIB_PAD_FROM_TO (0x581c, 0x5820);
592  CLIB_PAD_FROM_TO (0x5828, 0x5838);
594  CLIB_PAD_FROM_TO (0x583c, 0x5840);
595  u32 wake_up_ip4_address_table[4];
597  CLIB_PAD_FROM_TO (0x5854, 0x5880);
598  u32 wake_up_ip6_address_table[4];
599 
600  /* unicast_and broadcast_and vlan_and ip_address_and
601  etc. */
602  u32 management_decision_filters[8];
603 
604  u32 management_ip4_or_ip6_address_filters[4][4];
605  CLIB_PAD_FROM_TO (0x58f0, 0x5900);
607  CLIB_PAD_FROM_TO (0x5904, 0x5910);
608  u32 management_ethernet_address_filters[4][2];
609  CLIB_PAD_FROM_TO (0x5930, 0x5a00);
610  u32 wake_up_packet_memory[32];
611  CLIB_PAD_FROM_TO (0x5a80, 0x5c00);
612  u32 redirection_table_82598[32];
613  u32 rss_random_keys_82598[10];
614  CLIB_PAD_FROM_TO (0x5ca8, 0x6000);
615 
616  ixge_dma_regs_t tx_dma[128];
617 
618  u32 pf_vm_vlan_insert[64];
620  CLIB_PAD_FROM_TO (0x8104, 0x8110);
621  u32 vf_tx_enable[2];
622  CLIB_PAD_FROM_TO (0x8118, 0x8120);
623  /* [0] dcb mode enable
624  [1] virtualization mode enable
625  [3:2] number of tcs/qs per pool. */
627  CLIB_PAD_FROM_TO (0x8124, 0x8200);
628  u32 pf_vf_anti_spoof[8];
630  CLIB_PAD_FROM_TO (0x8224, 0x82e0);
631  u32 tx_strict_low_latency_queues[4];
632  CLIB_PAD_FROM_TO (0x82f0, 0x8600);
633  u32 tx_queue_stats_mapping_82599[32];
634  u32 tx_queue_packet_counts[32];
635  u32 tx_queue_byte_counts[32][2];
636 
637  struct
638  {
639  u32 control;
640  u32 status;
642  CLIB_PAD_FROM_TO (0x880c, 0x8810);
644  CLIB_PAD_FROM_TO (0x8814, 0x8900);
645  } tx_security;
646 
647  struct
648  {
651  u32 key[4];
652  CLIB_PAD_FROM_TO (0x8918, 0x8a00);
653  } tx_ipsec;
654 
655  struct
656  {
658  u32 control;
659  u32 tx_sci[2];
661  u32 sa_pn[2];
662  u32 key[2][4];
663  /* untagged packets, encrypted packets, protected packets,
664  encrypted bytes, protected bytes */
665  u32 stats[5];
666  CLIB_PAD_FROM_TO (0x8a50, 0x8c00);
667  } tx_link_security;
668 
669  struct
670  {
671  u32 control;
672  u32 timestamp_value[2];
673  u32 system_time[2];
675  u32 time_adjustment_offset[2];
677  u32 target_time[2][2];
678  CLIB_PAD_FROM_TO (0x8c34, 0x8c3c);
679  u32 aux_time_stamp[2][2];
680  CLIB_PAD_FROM_TO (0x8c4c, 0x8d00);
681  } tx_timesync;
682 
683  struct
684  {
685  u32 control;
686  u32 status;
687  CLIB_PAD_FROM_TO (0x8d08, 0x8e00);
688  } rx_security;
689 
690  struct
691  {
692  u32 index;
696  u32 key[4];
697  u32 salt;
699  CLIB_PAD_FROM_TO (0x8e34, 0x8f00);
700  } rx_ipsec;
701 
702  struct
703  {
704  u32 capabilities;
705  u32 control;
706  u32 sci[2];
707  u32 sa[2];
708  u32 sa_pn[2];
709  u32 key[2][4];
710  /* see datasheet */
711  u32 stats[17];
712  CLIB_PAD_FROM_TO (0x8f84, 0x9000);
713  } rx_link_security;
714 
715  /* 4 wake up, 2 management, 2 wake up. */
716  u32 flexible_filters[8][16][4];
717  CLIB_PAD_FROM_TO (0x9800, 0xa000);
718 
719  /* 4096 bits. */
720  u32 vlan_filter[128];
721 
722  /* [0] ethernet address [31:0]
723  [1] [15:0] ethernet address [47:32]
724  [31] valid bit.
725  Index 0 is read from eeprom after reset. */
726  u32 rx_ethernet_address1[128][2];
727 
728  /* select one of 64 pools for each rx address. */
729  u32 rx_ethernet_address_pool_select[128][2];
730  CLIB_PAD_FROM_TO (0xaa00, 0xc800);
732  CLIB_PAD_FROM_TO (0xc804, 0xcc00);
733 
734  /* In bytes units of 1k. Total packet buffer is 160k. */
735  u32 tx_packet_buffer_size[8];
736 
737  CLIB_PAD_FROM_TO (0xcc20, 0xcd10);
739  CLIB_PAD_FROM_TO (0xcd14, 0xcd20);
740  u32 dcb_tx_packet_plane_t2_config[8];
741  u32 dcb_tx_packet_plane_t2_status[8];
742  CLIB_PAD_FROM_TO (0xcd60, 0xce00);
743 
745  CLIB_PAD_FROM_TO (0xce04, 0xd000);
746 
747  ixge_dma_regs_t rx_dma1[64];
748 
749  struct
750  {
751  /* Bigendian ip4 src/dst address. */
753  u32 dst_address[128];
754 
755  /* TCP/UDP ports [15:0] src [31:16] dst; bigendian. */
756  u32 tcp_udp_port[128];
757 
758  /* [1:0] protocol tcp, udp, sctp, other
759  [4:2] match priority (highest wins)
760  [13:8] pool
761  [25] src address match disable
762  [26] dst address match disable
763  [27] src port match disable
764  [28] dst port match disable
765  [29] protocol match disable
766  [30] pool match disable
767  [31] enable. */
768  u32 control[128];
769 
770  /* [12] size bypass
771  [19:13] must be 0x80
772  [20] low-latency interrupt
773  [27:21] rx queue. */
774  u32 interrupt[128];
775  } ip4_filters;
776 
777  CLIB_PAD_FROM_TO (0xea00, 0xeb00);
778  /* 4 bit rss output index indexed by 7 bit hash.
779  128 8 bit fields = 32 registers. */
780  u32 redirection_table_82599[32];
781 
782  u32 rss_random_key_82599[10];
783  CLIB_PAD_FROM_TO (0xeba8, 0xec00);
784  /* [15:0] reserved
785  [22:16] rx queue index
786  [29] low-latency interrupt on match
787  [31] enable */
788  u32 ethernet_type_queue_select[8];
789  CLIB_PAD_FROM_TO (0xec20, 0xec30);
791  CLIB_PAD_FROM_TO (0xec34, 0xec60);
793  CLIB_PAD_FROM_TO (0xec64, 0xec70);
795  CLIB_PAD_FROM_TO (0xec74, 0xec90);
797  CLIB_PAD_FROM_TO (0xec94, 0xed00);
798 
799  struct
800  {
801  u32 control;
802  CLIB_PAD_FROM_TO (0xed04, 0xed10);
803  u32 table[8];
804  CLIB_PAD_FROM_TO (0xed30, 0xee00);
805  } fcoe_redirection;
806 
807  struct
808  {
809  /* [1:0] packet buffer allocation 0 => disabled, else 64k*2^(f-1)
810  [3] packet buffer initialization done
811  [4] perfetch match mode
812  [5] report status in rss field of rx descriptors
813  [7] report status always
814  [14:8] drop queue
815  [20:16] flex 2 byte packet offset (units of 2 bytes)
816  [27:24] max linked list length
817  [31:28] full threshold. */
818  u32 control;
819  CLIB_PAD_FROM_TO (0xee04, 0xee0c);
820 
821  u32 data[8];
822 
823  /* [1:0] 0 => no action, 1 => add, 2 => remove, 3 => query.
824  [2] valid filter found by query command
825  [3] filter update override
826  [4] ip6 adress table
827  [6:5] l4 protocol reserved, udp, tcp, sctp
828  [7] is ip6
829  [8] clear head/tail
830  [9] packet drop action
831  [10] matched packet generates low-latency interrupt
832  [11] last in linked list
833  [12] collision
834  [15] rx queue enable
835  [22:16] rx queue
836  [29:24] pool. */
838 
839  CLIB_PAD_FROM_TO (0xee30, 0xee3c);
840  /* ip4 dst/src address, tcp ports, udp ports.
841  set bits mean bit is ignored. */
842  u32 ip4_masks[4];
848  CLIB_PAD_FROM_TO (0xee60, 0xee68);
849  /* Lookup, signature. */
850  u32 hash_keys[2];
851  /* [15:0] ip6 src address 1 bit per byte
852  [31:16] ip6 dst address. */
854  /* [0] vlan id
855  [1] vlan priority
856  [2] pool
857  [3] ip protocol
858  [4] flex
859  [5] dst ip6. */
861  CLIB_PAD_FROM_TO (0xee78, 0xf000);
862  } flow_director;
863 
864  struct
865  {
866  u32 l2_control[64];
867  u32 vlan_pool_filter[64];
868  u32 vlan_pool_filter_bitmap[128];
869  u32 dst_ethernet_address[128];
870  u32 mirror_rule[4];
871  u32 mirror_rule_vlan[8];
872  u32 mirror_rule_pool[8];
873  CLIB_PAD_FROM_TO (0xf650, 0x10010);
874  } pf_bar;
875 
877  /* [0] start
878  [1] done
879  [15:2] address
880  [31:16] read data. */
882  CLIB_PAD_FROM_TO (0x10018, 0x1001c);
884  CLIB_PAD_FROM_TO (0x10020, 0x10114);
888  CLIB_PAD_FROM_TO (0x10120, 0x1013c);
891  CLIB_PAD_FROM_TO (0x10144, 0x10148);
893  CLIB_PAD_FROM_TO (0x1014c, 0x10160);
895  CLIB_PAD_FROM_TO (0x10164, 0x10200);
897  CLIB_PAD_FROM_TO (0x10204, 0x11000);
898 
899  struct
900  {
901  u32 control;
902  CLIB_PAD_FROM_TO (0x11004, 0x11010);
903  /* [3:0] enable counters
904  [7:4] leaky bucket counter mode
905  [29] reset
906  [30] stop
907  [31] start. */
909  /* [7:0],[15:8],[23:16],[31:24] event for counters 0-3.
910  event codes:
911  0x0 bad tlp
912  0x10 reqs that reached timeout
913  etc. */
915  CLIB_PAD_FROM_TO (0x11018, 0x11020);
916  u32 counters_clear_on_read[4];
917  u32 counter_config[4];
918  struct
919  {
921  u32 data;
922  } indirect_access;
923  CLIB_PAD_FROM_TO (0x11048, 0x11050);
924  u32 extended_control;
925  CLIB_PAD_FROM_TO (0x11054, 0x11064);
927  CLIB_PAD_FROM_TO (0x11068, 0x11070);
929 
930  /* [0] global disable
931  [4:1] mode: 0 => legacy, 1 => dca 1.0. */
933  CLIB_PAD_FROM_TO (0x11078, 0x110b0);
934  /* [0] pci completion abort
935  [1] unsupported i/o address
936  [2] wrong byte enable
937  [3] pci timeout */
939  CLIB_PAD_FROM_TO (0x110b4, 0x110b8);
941  CLIB_PAD_FROM_TO (0x110bc, 0x110c0);
942  u32 msi_x_pba_clear[8];
943  CLIB_PAD_FROM_TO (0x110e0, 0x12300);
944  } pcie;
945 
946  u32 interrupt_throttle1[128 - 24];
947  CLIB_PAD_FROM_TO (0x124a0, 0x14f00);
948 
950  CLIB_PAD_FROM_TO (0x14f04, 0x14f10);
952  CLIB_PAD_FROM_TO (0x14f14, 0x15f14);
953 
955 } ixge_regs_t;
956 
957 typedef union
958 {
959  struct
960  {
961  /* Addresses bigendian. */
962  union
963  {
964  struct
965  {
966  ip6_address_t src_address;
967  u32 unused[1];
968  } ip6;
969  struct
970  {
971  u32 unused[3];
973  } ip4;
974  };
975 
976  /* [15:0] src port (little endian).
977  [31:16] dst port. */
979 
980  /* [15:0] vlan (cfi bit set to 0).
981  [31:16] flex bytes. bigendian. */
983 
984  /* [14:0] hash
985  [15] bucket valid
986  [31:16] signature (signature filers)/sw-index (perfect match). */
988  };
989 
990  u32 as_u32[8];
992 
993 always_inline void
995  u32 queue_interrupt_index,
996  f64 inter_interrupt_interval_in_secs)
997 {
998  volatile u32 *tr =
999  (queue_interrupt_index < ARRAY_LEN (r->interrupt.throttle0)
1000  ? &r->interrupt.throttle0[queue_interrupt_index]
1001  : &r->interrupt_throttle1[queue_interrupt_index]);
1002  ASSERT (queue_interrupt_index < 128);
1003  u32 v;
1004  i32 i, mask = (1 << 9) - 1;
1005 
1006  i = flt_round_nearest (inter_interrupt_interval_in_secs / 2e-6);
1007  i = i < 1 ? 1 : i;
1008  i = i >= mask ? mask : i;
1009 
1010  v = tr[0];
1011  v &= ~(mask << 3);
1012  v |= i << 3;
1013  tr[0] = v;
1014 }
1015 
1016 #define foreach_ixge_counter \
1017  _ (0x40d0, rx_total_packets) \
1018  _64 (0x40c0, rx_total_bytes) \
1019  _ (0x41b0, rx_good_packets_before_filtering) \
1020  _64 (0x41b4, rx_good_bytes_before_filtering) \
1021  _ (0x2f50, rx_dma_good_packets) \
1022  _64 (0x2f54, rx_dma_good_bytes) \
1023  _ (0x2f5c, rx_dma_duplicated_good_packets) \
1024  _64 (0x2f60, rx_dma_duplicated_good_bytes) \
1025  _ (0x2f68, rx_dma_good_loopback_packets) \
1026  _64 (0x2f6c, rx_dma_good_loopback_bytes) \
1027  _ (0x2f74, rx_dma_good_duplicated_loopback_packets) \
1028  _64 (0x2f78, rx_dma_good_duplicated_loopback_bytes) \
1029  _ (0x4074, rx_good_packets) \
1030  _64 (0x4088, rx_good_bytes) \
1031  _ (0x407c, rx_multicast_packets) \
1032  _ (0x4078, rx_broadcast_packets) \
1033  _ (0x405c, rx_64_byte_packets) \
1034  _ (0x4060, rx_65_127_byte_packets) \
1035  _ (0x4064, rx_128_255_byte_packets) \
1036  _ (0x4068, rx_256_511_byte_packets) \
1037  _ (0x406c, rx_512_1023_byte_packets) \
1038  _ (0x4070, rx_gt_1023_byte_packets) \
1039  _ (0x4000, rx_crc_errors) \
1040  _ (0x4120, rx_ip_checksum_errors) \
1041  _ (0x4004, rx_illegal_symbol_errors) \
1042  _ (0x4008, rx_error_symbol_errors) \
1043  _ (0x4034, rx_mac_local_faults) \
1044  _ (0x4038, rx_mac_remote_faults) \
1045  _ (0x4040, rx_length_errors) \
1046  _ (0x41a4, rx_xons) \
1047  _ (0x41a8, rx_xoffs) \
1048  _ (0x40a4, rx_undersize_packets) \
1049  _ (0x40a8, rx_fragments) \
1050  _ (0x40ac, rx_oversize_packets) \
1051  _ (0x40b0, rx_jabbers) \
1052  _ (0x40b4, rx_management_packets) \
1053  _ (0x40b8, rx_management_drops) \
1054  _ (0x3fa0, rx_missed_packets_pool_0) \
1055  _ (0x40d4, tx_total_packets) \
1056  _ (0x4080, tx_good_packets) \
1057  _64 (0x4090, tx_good_bytes) \
1058  _ (0x40f0, tx_multicast_packets) \
1059  _ (0x40f4, tx_broadcast_packets) \
1060  _ (0x87a0, tx_dma_good_packets) \
1061  _64 (0x87a4, tx_dma_good_bytes) \
1062  _ (0x40d8, tx_64_byte_packets) \
1063  _ (0x40dc, tx_65_127_byte_packets) \
1064  _ (0x40e0, tx_128_255_byte_packets) \
1065  _ (0x40e4, tx_256_511_byte_packets) \
1066  _ (0x40e8, tx_512_1023_byte_packets) \
1067  _ (0x40ec, tx_gt_1023_byte_packets) \
1068  _ (0x4010, tx_undersize_drops) \
1069  _ (0x8780, switch_security_violation_packets) \
1070  _ (0x5118, fc_crc_errors) \
1071  _ (0x241c, fc_rx_drops) \
1072  _ (0x2424, fc_last_error_count) \
1073  _ (0x2428, fcoe_rx_packets) \
1074  _ (0x242c, fcoe_rx_dwords) \
1075  _ (0x8784, fcoe_tx_packets) \
1076  _ (0x8788, fcoe_tx_dwords) \
1077  _ (0x1030, queue_0_rx_count) \
1078  _ (0x1430, queue_0_drop_count) \
1079  _ (0x1070, queue_1_rx_count) \
1080  _ (0x1470, queue_1_drop_count) \
1081  _ (0x10b0, queue_2_rx_count) \
1082  _ (0x14b0, queue_2_drop_count) \
1083  _ (0x10f0, queue_3_rx_count) \
1084  _ (0x14f0, queue_3_drop_count) \
1085  _ (0x1130, queue_4_rx_count) \
1086  _ (0x1530, queue_4_drop_count) \
1087  _ (0x1170, queue_5_rx_count) \
1088  _ (0x1570, queue_5_drop_count) \
1089  _ (0x11b0, queue_6_rx_count) \
1090  _ (0x15b0, queue_6_drop_count) \
1091  _ (0x11f0, queue_7_rx_count) \
1092  _ (0x15f0, queue_7_drop_count) \
1093  _ (0x1230, queue_8_rx_count) \
1094  _ (0x1630, queue_8_drop_count) \
1095  _ (0x1270, queue_9_rx_count) \
1096  _ (0x1270, queue_9_drop_count)
1097 
1098 
1099 
1100 
1101 typedef enum
1102 {
1103 #define _(a,f) IXGE_COUNTER_##f,
1104 #define _64(a,f) _(a,f)
1106 #undef _
1107 #undef _64
1110 
1111 typedef struct
1112 {
1114 
1115  /* 32 bit ID read from ID registers. */
1117 } ixge_phy_t;
1118 
1119 typedef struct
1120 {
1121  /* Cache aligned descriptors. */
1123 
1124  /* Number of descriptors in table. */
1126 
1127  /* Software head and tail pointers into descriptor ring. */
1128  u32 head_index, tail_index;
1129 
1130  /* Index into dma_queues vector. */
1132 
1133  /* Buffer indices corresponding to each active descriptor. */
1135 
1136  union
1137  {
1138  struct
1139  {
1141 
1143  } tx;
1144 
1145  struct
1146  {
1147  /* Buffer indices to use to replenish each descriptor. */
1149 
1152 
1154 
1157 
1159 
1161 
1163 
1165  } rx;
1166  };
1168 
1169 #define foreach_ixge_pci_device_id \
1170  _ (82598, 0x10b6) \
1171  _ (82598_bx, 0x1508) \
1172  _ (82598af_dual_port, 0x10c6) \
1173  _ (82598af_single_port, 0x10c7) \
1174  _ (82598at, 0x10c8) \
1175  _ (82598at2, 0x150b) \
1176  _ (82598eb_sfp_lom, 0x10db) \
1177  _ (82598eb_cx4, 0x10dd) \
1178  _ (82598_cx4_dual_port, 0x10ec) \
1179  _ (82598_da_dual_port, 0x10f1) \
1180  _ (82598_sr_dual_port_em, 0x10e1) \
1181  _ (82598eb_xf_lr, 0x10f4) \
1182  _ (82599_kx4, 0x10f7) \
1183  _ (82599_kx4_mezz, 0x1514) \
1184  _ (82599_kr, 0x1517) \
1185  _ (82599_combo_backplane, 0x10f8) \
1186  _ (82599_cx4, 0x10f9) \
1187  _ (82599_sfp, 0x10fb) \
1188  _ (82599_backplane_fcoe, 0x152a) \
1189  _ (82599_sfp_fcoe, 0x1529) \
1190  _ (82599_sfp_em, 0x1507) \
1191  _ (82599_xaui_lom, 0x10fc) \
1192  _ (82599_t3_lom, 0x151c) \
1193  _ (x540t, 0x1528)
1194 
1195 typedef enum
1196 {
1197 #define _(f,n) IXGE_##f = n,
1199 #undef _
1201 
1202 typedef struct
1203 {
1204  /* registers */
1206 
1207  /* Specific next index when using dynamic redirection */
1209 
1210  /* PCI bus info. */
1212 
1213  /* From PCI config space header. */
1215 
1217 
1218  /* 0 or 1. */
1220 
1221  /* VLIB interface for this instance. */
1222  u32 vlib_hw_if_index, vlib_sw_if_index;
1223 
1225 
1226  /* Phy index (0 or 1) and address on MDI bus. */
1228  ixge_phy_t phys[2];
1229 
1230  /* Value of link_status register at last link change. */
1232 
1235 
1236  /* Counters. */
1237  u64 counters[IXGE_N_COUNTER], counters_last_clear[IXGE_N_COUNTER];
1238 } ixge_device_t;
1239 
1240 typedef struct
1241 {
1243 
1244  /* Vector of devices. */
1246 
1247  /* Descriptor ring sizes. */
1248  u32 n_descriptors[VLIB_N_RX_TX];
1249 
1250  /* RX buffer size. Must be at least 1k; will be rounded to
1251  next largest 1k size. */
1253 
1255 
1257 
1258  /* Template and mask for initializing/validating TX descriptors. */
1260 
1261  /* Vector of buffers for which TX is done and can be freed. */
1263 
1265 
1267 
1268 } ixge_main_t;
1269 
1270 extern ixge_main_t ixge_main;
1272 
1273 typedef enum
1274 {
1280 } ixge_rx_next_t;
1281 
1282 void ixge_set_next_node (ixge_rx_next_t, char *);
1283 
1284 #endif /* included_ixge_h */
1285 
1286 /*
1287  * fd.io coding-style-patch-verification: ON
1288  *
1289  * Local Variables:
1290  * eval: (c-set-style "gnu")
1291  * End:
1292  */
i2c_bus_t
Definition: i2c.h:33
ixge_regs_t::extended_vlan_ether_type
u32 extended_vlan_ether_type
Definition: ixge.h:516
ip_address
Definition: ip_types.h:79
ixge_descriptor_t::as_u32x4
u32x4 as_u32x4
Definition: ixge.h:171
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Definition: ixge.h:40
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u32 eeprom_flash_control
Definition: ixge.h:876
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u8 status1
Definition: ixge.h:158
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u32 tcp_udp_ports
Definition: ixge.h:978
ixge_regs_t::rss_queues_per_traffic_class
u32 rss_queues_per_traffic_class
Definition: ixge.h:794
ixge_device_t::sfp_eeprom
sfp_eeprom_t sfp_eeprom
Definition: ixge.h:1234
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u32 flow_control_refresh_threshold
Definition: ixge.h:327
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u32 auto_negotiation_control
Definition: ixge.h:427
ixge_regs_t::pf_queue_drop_enable
u32 pf_queue_drop_enable
Definition: ixge.h:302
ixge_regs_t::link_status
u32 link_status
Definition: ixge.h:340
ixge_regs_t::auto_negotiation_control2
u32 auto_negotiation_control2
Definition: ixge.h:465
ixge_regs_t::control_alias
u32 control_alias
Definition: ixge.h:180
ixge_regs_t::fc_flt_context
u32 fc_flt_context
Definition: ixge.h:538
ixge_dma_queue_t::replenish_buffer_indices
u32 * replenish_buffer_indices
Definition: ixge.h:1148
ixge_rx_to_hw_descriptor_t::tail_address
u64 tail_address
Definition: ixge.h:89
ixge_dma_queue_t::head_index_write_back
u32 *volatile head_index_write_back
Definition: ixge.h:1140
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u32 fifo_control
Definition: ixge.h:404
ixge_regs_t::tx_flow_control_status
u32 tx_flow_control_status
Definition: ixge.h:744
vnet_device_class_t
struct _vnet_device_class vnet_device_class_t
ixge_regs_t::core_common_config
u32 core_common_config
Definition: ixge.h:951
ixge_device_t::device_index
u16 device_index
Definition: ixge.h:1216
ixge_regs_t::index
u32 index
Definition: ixge.h:649
ixge_regs_t::phy_data
u32 phy_data
Definition: ixge.h:369
ixge_regs_t::sa
u32 sa
Definition: ixge.h:660
ixge_tx_context_descriptor_t::checksum_end_offset
u16 checksum_end_offset
Definition: ixge.h:154
IXGE_RX_N_NEXT
@ IXGE_RX_N_NEXT
Definition: ixge.h:1279
ip4
vl_api_ip4_address_t ip4
Definition: one.api:376
ixge_tx_descriptor_t::buffer_address
u64 buffer_address
Definition: ixge.h:128
ixge_regs_t::tx_dma_control
u32 tx_dma_control
Definition: ixge.h:500
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@ IXGE_RX_NEXT_IP4_INPUT
Definition: ixge.h:1275
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Definition: ixge.h:694
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Definition: ixge.h:695
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Definition: ixge.h:394
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Definition: ixge.h:641
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#define ARRAY_LEN(x)
Definition: clib.h:70
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i
sll srl srl sll sra u16x4 i
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f64
double f64
Definition: types.h:142
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Definition: pnat.api:45
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Definition: ixge.h:250
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Definition: ixge.h:1202
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Definition: ip4_packet.h:50
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Definition: ixge.h:1231
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Definition: ixge.h:388
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IXGE_N_COUNTER
@ IXGE_N_COUNTER
Definition: ixge.h:1108
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Definition: ixge.h:30
VLIB_N_RX_TX
@ VLIB_N_RX_TX
Definition: defs.h:48
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Definition: ixge.h:568
data
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Definition: ipsec_types.api:92
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Definition: ixge.h:1134
IXGE_RX_NEXT_DROP
@ IXGE_RX_NEXT_DROP
Definition: ixge.h:1278
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Definition: ixge.h:966
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Definition: ixge.h:130
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Definition: ixge.h:366
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Definition: ixge.h:1153
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Definition: ixge.h:486
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Definition: ixge.h:796
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Definition: ixge.h:844
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Definition: ixge.h:1169
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Definition: ixge.h:1240
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Definition: ixge.h:192
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Definition: types.h:89
IXGE_RX_NEXT_ETHERNET_INPUT
@ IXGE_RX_NEXT_ETHERNET_INPUT
Definition: ixge.h:1277
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Definition: error_bootstrap.h:69
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Definition: ixge.h:1266
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Definition: ixge.h:96
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Definition: ixge.h:1164
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Definition: ixge.h:860
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Definition: ixge.h:883
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Definition: one.api:424
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u32 tx_manageability_tc_mapping
Definition: ixge.h:738
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Definition: ixge.h:1211
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void ixge_set_next_node(ixge_rx_next_t, char *)
Definition: ixge.c:2891
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Definition: ipsec_types.api:136
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Definition: ixge.h:179
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Definition: l2.api:558
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Definition: ixge.h:1195
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Definition: ixge.h:957
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Definition: node.h:454
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Definition: ip_types.api:122
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static void ixge_throttle_queue_interrupt(ixge_regs_t *r, u32 queue_interrupt_index, f64 inter_interrupt_interval_in_secs)
Definition: ixge.h:994
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Definition: ixge.h:214
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Definition: ixge.h:522
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Definition: ixge.h:1222