FD.io VPP
v21.10.1-2-g0a485f517
Vector Packet Processing
perfmon_intel_bdw.c
Go to the documentation of this file.
1
2
#include <
perfmon/perfmon_intel.h
>
3
4
static
perfmon_intel_pmc_cpu_model_t
cpu_model_table
[] = {
5
{0x3D, 0x00, 0},
6
{0x47, 0x00, 0},
7
8
};
9
10
static
perfmon_intel_pmc_event_t
event_table
[] = {
11
{
12
.
event_code
= {0x00},
13
.umask = 0x01,
14
.event_name =
"inst_retired.any"
,
15
},
16
{
17
.event_code = {0x00},
18
.umask = 0x02,
19
.event_name =
"cpu_clk_unhalted.thread"
,
20
},
21
{
22
.event_code = {0x00},
23
.umask = 0x02,
24
.event_name =
"cpu_clk_unhalted.thread_any"
,
25
},
26
{
27
.event_code = {0x00},
28
.umask = 0x03,
29
.event_name =
"cpu_clk_unhalted.ref_tsc"
,
30
},
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{
32
.event_code = {0x03},
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.umask = 0x02,
34
.event_name =
"ld_blocks.store_forward"
,
35
},
36
{
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.event_code = {0x03},
38
.umask = 0x08,
39
.event_name =
"ld_blocks.no_sr"
,
40
},
41
{
42
.event_code = {0x05},
43
.umask = 0x01,
44
.event_name =
"misalign_mem_ref.loads"
,
45
},
46
{
47
.event_code = {0x05},
48
.umask = 0x02,
49
.event_name =
"misalign_mem_ref.stores"
,
50
},
51
{
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.event_code = {0x07},
53
.umask = 0x01,
54
.event_name =
"ld_blocks_partial.address_alias"
,
55
},
56
{
57
.event_code = {0x08},
58
.umask = 0x01,
59
.event_name =
"dtlb_load_misses.miss_causes_a_walk"
,
60
},
61
{
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.event_code = {0x08},
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.umask = 0x02,
64
.event_name =
"dtlb_load_misses.walk_completed_4k"
,
65
},
66
{
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.event_code = {0x08},
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.umask = 0x04,
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.event_name =
"dtlb_load_misses.walk_completed_2m_4m"
,
70
},
71
{
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.event_code = {0x08},
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.umask = 0x08,
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.event_name =
"dtlb_load_misses.walk_completed_1g"
,
75
},
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{
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.event_code = {0x08},
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.umask = 0x0e,
79
.event_name =
"dtlb_load_misses.walk_completed"
,
80
},
81
{
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.event_code = {0x08},
83
.umask = 0x10,
84
.event_name =
"dtlb_load_misses.walk_duration"
,
85
},
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{
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.event_code = {0x08},
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.umask = 0x20,
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.event_name =
"dtlb_load_misses.stlb_hit_4k"
,
90
},
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{
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.event_code = {0x08},
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.umask = 0x40,
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.event_name =
"dtlb_load_misses.stlb_hit_2m"
,
95
},
96
{
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.event_code = {0x08},
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.umask = 0x60,
99
.event_name =
"dtlb_load_misses.stlb_hit"
,
100
},
101
{
102
.event_code = {0x0D},
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.umask = 0x03,
104
.event_name =
"int_misc.recovery_cycles"
,
105
},
106
{
107
.event_code = {0x0D},
108
.umask = 0x03,
109
.event_name =
"int_misc.recovery_cycles_any"
,
110
},
111
{
112
.event_code = {0x0D},
113
.umask = 0x08,
114
.event_name =
"int_misc.rat_stall_cycles"
,
115
},
116
{
117
.event_code = {0x0E},
118
.umask = 0x01,
119
.event_name =
"uops_issued.any"
,
120
},
121
{
122
.event_code = {0x0E},
123
.umask = 0x01,
124
.event_name =
"uops_issued.stall_cycles"
,
125
},
126
{
127
.event_code = {0x0E},
128
.umask = 0x10,
129
.event_name =
"uops_issued.flags_merge"
,
130
},
131
{
132
.event_code = {0x0E},
133
.umask = 0x20,
134
.event_name =
"uops_issued.slow_lea"
,
135
},
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{
137
.event_code = {0x0E},
138
.umask = 0x40,
139
.event_name =
"uops_issued.single_mul"
,
140
},
141
{
142
.event_code = {0x14},
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.umask = 0x01,
144
.event_name =
"arith.fpu_div_active"
,
145
},
146
{
147
.event_code = {0x24},
148
.umask = 0x21,
149
.event_name =
"l2_rqsts.demand_data_rd_miss"
,
150
},
151
{
152
.event_code = {0x24},
153
.umask = 0x22,
154
.event_name =
"l2_rqsts.rfo_miss"
,
155
},
156
{
157
.event_code = {0x24},
158
.umask = 0x24,
159
.event_name =
"l2_rqsts.code_rd_miss"
,
160
},
161
{
162
.event_code = {0x24},
163
.umask = 0x27,
164
.event_name =
"l2_rqsts.all_demand_miss"
,
165
},
166
{
167
.event_code = {0x24},
168
.umask = 0x30,
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.event_name =
"l2_rqsts.l2_pf_miss"
,
170
},
171
{
172
.event_code = {0x24},
173
.umask = 0x3F,
174
.event_name =
"l2_rqsts.miss"
,
175
},
176
{
177
.event_code = {0x24},
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.umask = 0xc1,
179
.event_name =
"l2_rqsts.demand_data_rd_hit"
,
180
},
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{
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.event_code = {0x24},
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.umask = 0xc2,
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.event_name =
"l2_rqsts.rfo_hit"
,
185
},
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{
187
.event_code = {0x24},
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.umask = 0xc4,
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.event_name =
"l2_rqsts.code_rd_hit"
,
190
},
191
{
192
.event_code = {0x24},
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.umask = 0xd0,
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.event_name =
"l2_rqsts.l2_pf_hit"
,
195
},
196
{
197
.event_code = {0x24},
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.umask = 0xE1,
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.event_name =
"l2_rqsts.all_demand_data_rd"
,
200
},
201
{
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.event_code = {0x24},
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.umask = 0xE2,
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.event_name =
"l2_rqsts.all_rfo"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xE4,
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.event_name =
"l2_rqsts.all_code_rd"
,
210
},
211
{
212
.event_code = {0x24},
213
.umask = 0xe7,
214
.event_name =
"l2_rqsts.all_demand_references"
,
215
},
216
{
217
.event_code = {0x24},
218
.umask = 0xF8,
219
.event_name =
"l2_rqsts.all_pf"
,
220
},
221
{
222
.event_code = {0x24},
223
.umask = 0xFF,
224
.event_name =
"l2_rqsts.references"
,
225
},
226
{
227
.event_code = {0x27},
228
.umask = 0x50,
229
.event_name =
"l2_demand_rqsts.wb_hit"
,
230
},
231
{
232
.event_code = {0x2E},
233
.umask = 0x41,
234
.event_name =
"longest_lat_cache.miss"
,
235
},
236
{
237
.event_code = {0x2E},
238
.umask = 0x4F,
239
.event_name =
"longest_lat_cache.reference"
,
240
},
241
{
242
.event_code = {0x3C},
243
.umask = 0x00,
244
.event_name =
"cpu_clk_unhalted.thread_p"
,
245
},
246
{
247
.event_code = {0x3C},
248
.umask = 0x00,
249
.event_name =
"cpu_clk_unhalted.thread_p_any"
,
250
},
251
{
252
.event_code = {0x3C},
253
.umask = 0x01,
254
.event_name =
"cpu_clk_thread_unhalted.ref_xclk"
,
255
},
256
{
257
.event_code = {0x3C},
258
.umask = 0x01,
259
.event_name =
"cpu_clk_thread_unhalted.ref_xclk_any"
,
260
},
261
{
262
.event_code = {0x3c},
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.umask = 0x02,
264
.event_name =
"cpu_clk_thread_unhalted.one_thread_active"
,
265
},
266
{
267
.event_code = {0x48},
268
.umask = 0x01,
269
.event_name =
"l1d_pend_miss.pending"
,
270
},
271
{
272
.event_code = {0x48},
273
.umask = 0x01,
274
.event_name =
"l1d_pend_miss.pending_cycles"
,
275
},
276
{
277
.event_code = {0x49},
278
.umask = 0x01,
279
.event_name =
"dtlb_store_misses.miss_causes_a_walk"
,
280
},
281
{
282
.event_code = {0x49},
283
.umask = 0x02,
284
.event_name =
"dtlb_store_misses.walk_completed_4k"
,
285
},
286
{
287
.event_code = {0x49},
288
.umask = 0x04,
289
.event_name =
"dtlb_store_misses.walk_completed_2m_4m"
,
290
},
291
{
292
.event_code = {0x49},
293
.umask = 0x08,
294
.event_name =
"dtlb_store_misses.walk_completed_1g"
,
295
},
296
{
297
.event_code = {0x49},
298
.umask = 0x0e,
299
.event_name =
"dtlb_store_misses.walk_completed"
,
300
},
301
{
302
.event_code = {0x49},
303
.umask = 0x10,
304
.event_name =
"dtlb_store_misses.walk_duration"
,
305
},
306
{
307
.event_code = {0x49},
308
.umask = 0x20,
309
.event_name =
"dtlb_store_misses.stlb_hit_4k"
,
310
},
311
{
312
.event_code = {0x49},
313
.umask = 0x40,
314
.event_name =
"dtlb_store_misses.stlb_hit_2m"
,
315
},
316
{
317
.event_code = {0x49},
318
.umask = 0x60,
319
.event_name =
"dtlb_store_misses.stlb_hit"
,
320
},
321
{
322
.event_code = {0x4c},
323
.umask = 0x01,
324
.event_name =
"load_hit_pre.sw_pf"
,
325
},
326
{
327
.event_code = {0x4C},
328
.umask = 0x02,
329
.event_name =
"load_hit_pre.hw_pf"
,
330
},
331
{
332
.event_code = {0x4F},
333
.umask = 0x10,
334
.event_name =
"ept.walk_cycles"
,
335
},
336
{
337
.event_code = {0x51},
338
.umask = 0x01,
339
.event_name =
"l1d.replacement"
,
340
},
341
{
342
.event_code = {0x54},
343
.umask = 0x01,
344
.event_name =
"tx_mem.abort_conflict"
,
345
},
346
{
347
.event_code = {0x54},
348
.umask = 0x02,
349
.event_name =
"tx_mem.abort_capacity_write"
,
350
},
351
{
352
.event_code = {0x54},
353
.umask = 0x04,
354
.event_name =
"tx_mem.abort_hle_store_to_elided_lock"
,
355
},
356
{
357
.event_code = {0x54},
358
.umask = 0x08,
359
.event_name =
"tx_mem.abort_hle_elision_buffer_not_empty"
,
360
},
361
{
362
.event_code = {0x54},
363
.umask = 0x10,
364
.event_name =
"tx_mem.abort_hle_elision_buffer_mismatch"
,
365
},
366
{
367
.event_code = {0x54},
368
.umask = 0x20,
369
.event_name =
"tx_mem.abort_hle_elision_buffer_unsupported_alignment"
,
370
},
371
{
372
.event_code = {0x54},
373
.umask = 0x40,
374
.event_name =
"tx_mem.hle_elision_buffer_full"
,
375
},
376
{
377
.event_code = {0x58},
378
.umask = 0x01,
379
.event_name =
"move_elimination.int_eliminated"
,
380
},
381
{
382
.event_code = {0x58},
383
.umask = 0x02,
384
.event_name =
"move_elimination.simd_eliminated"
,
385
},
386
{
387
.event_code = {0x58},
388
.umask = 0x04,
389
.event_name =
"move_elimination.int_not_eliminated"
,
390
},
391
{
392
.event_code = {0x58},
393
.umask = 0x08,
394
.event_name =
"move_elimination.simd_not_eliminated"
,
395
},
396
{
397
.event_code = {0x5C},
398
.umask = 0x01,
399
.event_name =
"cpl_cycles.ring0"
,
400
},
401
{
402
.event_code = {0x5C},
403
.umask = 0x01,
404
.event_name =
"cpl_cycles.ring0_trans"
,
405
},
406
{
407
.event_code = {0x5C},
408
.umask = 0x02,
409
.event_name =
"cpl_cycles.ring123"
,
410
},
411
{
412
.event_code = {0x5d},
413
.umask = 0x01,
414
.event_name =
"tx_exec.misc1"
,
415
},
416
{
417
.event_code = {0x5d},
418
.umask = 0x02,
419
.event_name =
"tx_exec.misc2"
,
420
},
421
{
422
.event_code = {0x5d},
423
.umask = 0x04,
424
.event_name =
"tx_exec.misc3"
,
425
},
426
{
427
.event_code = {0x5d},
428
.umask = 0x08,
429
.event_name =
"tx_exec.misc4"
,
430
},
431
{
432
.event_code = {0x5d},
433
.umask = 0x10,
434
.event_name =
"tx_exec.misc5"
,
435
},
436
{
437
.event_code = {0x5E},
438
.umask = 0x01,
439
.event_name =
"rs_events.empty_cycles"
,
440
},
441
{
442
.event_code = {0x5E},
443
.umask = 0x01,
444
.event_name =
"rs_events.empty_end"
,
445
},
446
{
447
.event_code = {0x60},
448
.umask = 0x01,
449
.event_name =
"offcore_requests_outstanding.demand_data_rd"
,
450
},
451
{
452
.event_code = {0x60},
453
.umask = 0x01,
454
.event_name =
"offcore_requests_outstanding.cycles_with_demand_data_rd"
,
455
},
456
{
457
.event_code = {0x60},
458
.umask = 0x02,
459
.event_name =
"offcore_requests_outstanding.demand_code_rd"
,
460
},
461
{
462
.event_code = {0x60},
463
.umask = 0x04,
464
.event_name =
"offcore_requests_outstanding.demand_rfo"
,
465
},
466
{
467
.event_code = {0x60},
468
.umask = 0x04,
469
.event_name =
"offcore_requests_outstanding.cycles_with_demand_rfo"
,
470
},
471
{
472
.event_code = {0x60},
473
.umask = 0x08,
474
.event_name =
"offcore_requests_outstanding.all_data_rd"
,
475
},
476
{
477
.event_code = {0x60},
478
.umask = 0x08,
479
.event_name =
"offcore_requests_outstanding.cycles_with_data_rd"
,
480
},
481
{
482
.event_code = {0x63},
483
.umask = 0x01,
484
.event_name =
"lock_cycles.split_lock_uc_lock_duration"
,
485
},
486
{
487
.event_code = {0x63},
488
.umask = 0x02,
489
.event_name =
"lock_cycles.cache_lock_duration"
,
490
},
491
{
492
.event_code = {0x79},
493
.umask = 0x02,
494
.event_name =
"idq.empty"
,
495
},
496
{
497
.event_code = {0x79},
498
.umask = 0x04,
499
.event_name =
"idq.mite_uops"
,
500
},
501
{
502
.event_code = {0x79},
503
.umask = 0x04,
504
.event_name =
"idq.mite_cycles"
,
505
},
506
{
507
.event_code = {0x79},
508
.umask = 0x08,
509
.event_name =
"idq.dsb_uops"
,
510
},
511
{
512
.event_code = {0x79},
513
.umask = 0x08,
514
.event_name =
"idq.dsb_cycles"
,
515
},
516
{
517
.event_code = {0x79},
518
.umask = 0x10,
519
.event_name =
"idq.ms_dsb_uops"
,
520
},
521
{
522
.event_code = {0x79},
523
.umask = 0x10,
524
.event_name =
"idq.ms_dsb_cycles"
,
525
},
526
{
527
.event_code = {0x79},
528
.umask = 0x10,
529
.event_name =
"idq.ms_dsb_occur"
,
530
},
531
{
532
.event_code = {0x79},
533
.umask = 0x18,
534
.event_name =
"idq.all_dsb_cycles_4_uops"
,
535
},
536
{
537
.event_code = {0x79},
538
.umask = 0x18,
539
.event_name =
"idq.all_dsb_cycles_any_uops"
,
540
},
541
{
542
.event_code = {0x79},
543
.umask = 0x20,
544
.event_name =
"idq.ms_mite_uops"
,
545
},
546
{
547
.event_code = {0x79},
548
.umask = 0x24,
549
.event_name =
"idq.all_mite_cycles_4_uops"
,
550
},
551
{
552
.event_code = {0x79},
553
.umask = 0x24,
554
.event_name =
"idq.all_mite_cycles_any_uops"
,
555
},
556
{
557
.event_code = {0x79},
558
.umask = 0x30,
559
.event_name =
"idq.ms_uops"
,
560
},
561
{
562
.event_code = {0x79},
563
.umask = 0x30,
564
.event_name =
"idq.ms_cycles"
,
565
},
566
{
567
.event_code = {0x79},
568
.umask = 0x30,
569
.event_name =
"idq.ms_switches"
,
570
},
571
{
572
.event_code = {0x79},
573
.umask = 0x3C,
574
.event_name =
"idq.mite_all_uops"
,
575
},
576
{
577
.event_code = {0x80},
578
.umask = 0x01,
579
.event_name =
"icache.hit"
,
580
},
581
{
582
.event_code = {0x80},
583
.umask = 0x02,
584
.event_name =
"icache.misses"
,
585
},
586
{
587
.event_code = {0x80},
588
.umask = 0x04,
589
.event_name =
"icache.ifdata_stall"
,
590
},
591
{
592
.event_code = {0x85},
593
.umask = 0x01,
594
.event_name =
"itlb_misses.miss_causes_a_walk"
,
595
},
596
{
597
.event_code = {0x85},
598
.umask = 0x02,
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.umask = 0x04,
1174
.event_name =
"machine_clears.smc"
,
1175
},
1176
{
1177
.event_code = {0xC3},
1178
.umask = 0x20,
1179
.event_name =
"machine_clears.maskmov"
,
1180
},
1181
{
1182
.event_code = {0xC4},
1183
.umask = 0x00,
1184
.event_name =
"br_inst_retired.all_branches"
,
1185
},
1186
{
1187
.event_code = {0xC4},
1188
.umask = 0x01,
1189
.event_name =
"br_inst_retired.conditional"
,
1190
},
1191
{
1192
.event_code = {0xC4},
1193
.umask = 0x02,
1194
.event_name =
"br_inst_retired.near_call"
,
1195
},
1196
{
1197
.event_code = {0xC4},
1198
.umask = 0x02,
1199
.event_name =
"br_inst_retired.near_call_r3"
,
1200
},
1201
{
1202
.event_code = {0xC4},
1203
.umask = 0x04,
1204
.event_name =
"br_inst_retired.all_branches_pebs"
,
1205
},
1206
{
1207
.event_code = {0xC4},
1208
.umask = 0x08,
1209
.event_name =
"br_inst_retired.near_return"
,
1210
},
1211
{
1212
.event_code = {0xC4},
1213
.umask = 0x10,
1214
.event_name =
"br_inst_retired.not_taken"
,
1215
},
1216
{
1217
.event_code = {0xC4},
1218
.umask = 0x20,
1219
.event_name =
"br_inst_retired.near_taken"
,
1220
},
1221
{
1222
.event_code = {0xC4},
1223
.umask = 0x40,
1224
.event_name =
"br_inst_retired.far_branch"
,
1225
},
1226
{
1227
.event_code = {0xC5},
1228
.umask = 0x00,
1229
.event_name =
"br_misp_retired.all_branches"
,
1230
},
1231
{
1232
.event_code = {0xC5},
1233
.umask = 0x01,
1234
.event_name =
"br_misp_retired.conditional"
,
1235
},
1236
{
1237
.event_code = {0xC5},
1238
.umask = 0x04,
1239
.event_name =
"br_misp_retired.all_branches_pebs"
,
1240
},
1241
{
1242
.event_code = {0xC5},
1243
.umask = 0x08,
1244
.event_name =
"br_misp_retired.ret"
,
1245
},
1246
{
1247
.event_code = {0xC5},
1248
.umask = 0x20,
1249
.event_name =
"br_misp_retired.near_taken"
,
1250
},
1251
{
1252
.event_code = {0xC7},
1253
.umask = 0x01,
1254
.event_name =
"fp_arith_inst_retired.scalar_double"
,
1255
},
1256
{
1257
.event_code = {0xC7},
1258
.umask = 0x02,
1259
.event_name =
"fp_arith_inst_retired.scalar_single"
,
1260
},
1261
{
1262
.event_code = {0xC7},
1263
.umask = 0x04,
1264
.event_name =
"fp_arith_inst_retired.128b_packed_double"
,
1265
},
1266
{
1267
.event_code = {0xC7},
1268
.umask = 0x08,
1269
.event_name =
"fp_arith_inst_retired.128b_packed_single"
,
1270
},
1271
{
1272
.event_code = {0xC7},
1273
.umask = 0x10,
1274
.event_name =
"fp_arith_inst_retired.256b_packed_double"
,
1275
},
1276
{
1277
.event_code = {0xc7},
1278
.umask = 0x20,
1279
.event_name =
"fp_arith_inst_retired.256b_packed_single"
,
1280
},
1281
{
1282
.event_code = {0xc8},
1283
.umask = 0x01,
1284
.event_name =
"hle_retired.start"
,
1285
},
1286
{
1287
.event_code = {0xc8},
1288
.umask = 0x02,
1289
.event_name =
"hle_retired.commit"
,
1290
},
1291
{
1292
.event_code = {0xc8},
1293
.umask = 0x04,
1294
.event_name =
"hle_retired.aborted"
,
1295
},
1296
{
1297
.event_code = {0xc8},
1298
.umask = 0x08,
1299
.event_name =
"hle_retired.aborted_misc1"
,
1300
},
1301
{
1302
.event_code = {0xc8},
1303
.umask = 0x10,
1304
.event_name =
"hle_retired.aborted_misc2"
,
1305
},
1306
{
1307
.event_code = {0xc8},
1308
.umask = 0x20,
1309
.event_name =
"hle_retired.aborted_misc3"
,
1310
},
1311
{
1312
.event_code = {0xc8},
1313
.umask = 0x40,
1314
.event_name =
"hle_retired.aborted_misc4"
,
1315
},
1316
{
1317
.event_code = {0xc8},
1318
.umask = 0x80,
1319
.event_name =
"hle_retired.aborted_misc5"
,
1320
},
1321
{
1322
.event_code = {0xc9},
1323
.umask = 0x01,
1324
.event_name =
"rtm_retired.start"
,
1325
},
1326
{
1327
.event_code = {0xc9},
1328
.umask = 0x02,
1329
.event_name =
"rtm_retired.commit"
,
1330
},
1331
{
1332
.event_code = {0xc9},
1333
.umask = 0x04,
1334
.event_name =
"rtm_retired.aborted"
,
1335
},
1336
{
1337
.event_code = {0xc9},
1338
.umask = 0x08,
1339
.event_name =
"rtm_retired.aborted_misc1"
,
1340
},
1341
{
1342
.event_code = {0xc9},
1343
.umask = 0x10,
1344
.event_name =
"rtm_retired.aborted_misc2"
,
1345
},
1346
{
1347
.event_code = {0xc9},
1348
.umask = 0x20,
1349
.event_name =
"rtm_retired.aborted_misc3"
,
1350
},
1351
{
1352
.event_code = {0xc9},
1353
.umask = 0x40,
1354
.event_name =
"rtm_retired.aborted_misc4"
,
1355
},
1356
{
1357
.event_code = {0xc9},
1358
.umask = 0x80,
1359
.event_name =
"rtm_retired.aborted_misc5"
,
1360
},
1361
{
1362
.event_code = {0xCA},
1363
.umask = 0x02,
1364
.event_name =
"fp_assist.x87_output"
,
1365
},
1366
{
1367
.event_code = {0xCA},
1368
.umask = 0x04,
1369
.event_name =
"fp_assist.x87_input"
,
1370
},
1371
{
1372
.event_code = {0xCA},
1373
.umask = 0x08,
1374
.event_name =
"fp_assist.simd_output"
,
1375
},
1376
{
1377
.event_code = {0xCA},
1378
.umask = 0x10,
1379
.event_name =
"fp_assist.simd_input"
,
1380
},
1381
{
1382
.event_code = {0xCA},
1383
.umask = 0x1E,
1384
.event_name =
"fp_assist.any"
,
1385
},
1386
{
1387
.event_code = {0xCC},
1388
.umask = 0x20,
1389
.event_name =
"rob_misc_events.lbr_inserts"
,
1390
},
1391
{
1392
.event_code = {0xD0},
1393
.umask = 0x11,
1394
.event_name =
"mem_uops_retired.stlb_miss_loads"
,
1395
},
1396
{
1397
.event_code = {0xD0},
1398
.umask = 0x12,
1399
.event_name =
"mem_uops_retired.stlb_miss_stores"
,
1400
},
1401
{
1402
.event_code = {0xD0},
1403
.umask = 0x21,
1404
.event_name =
"mem_uops_retired.lock_loads"
,
1405
},
1406
{
1407
.event_code = {0xD0},
1408
.umask = 0x41,
1409
.event_name =
"mem_uops_retired.split_loads"
,
1410
},
1411
{
1412
.event_code = {0xD0},
1413
.umask = 0x42,
1414
.event_name =
"mem_uops_retired.split_stores"
,
1415
},
1416
{
1417
.event_code = {0xD0},
1418
.umask = 0x81,
1419
.event_name =
"mem_uops_retired.all_loads"
,
1420
},
1421
{
1422
.event_code = {0xD0},
1423
.umask = 0x82,
1424
.event_name =
"mem_uops_retired.all_stores"
,
1425
},
1426
{
1427
.event_code = {0xD1},
1428
.umask = 0x01,
1429
.event_name =
"mem_load_uops_retired.l1_hit"
,
1430
},
1431
{
1432
.event_code = {0xD1},
1433
.umask = 0x02,
1434
.event_name =
"mem_load_uops_retired.l2_hit"
,
1435
},
1436
{
1437
.event_code = {0xD1},
1438
.umask = 0x04,
1439
.event_name =
"mem_load_uops_retired.l3_hit"
,
1440
},
1441
{
1442
.event_code = {0xD1},
1443
.umask = 0x08,
1444
.event_name =
"mem_load_uops_retired.l1_miss"
,
1445
},
1446
{
1447
.event_code = {0xD1},
1448
.umask = 0x10,
1449
.event_name =
"mem_load_uops_retired.l2_miss"
,
1450
},
1451
{
1452
.event_code = {0xD1},
1453
.umask = 0x20,
1454
.event_name =
"mem_load_uops_retired.l3_miss"
,
1455
},
1456
{
1457
.event_code = {0xD1},
1458
.umask = 0x40,
1459
.event_name =
"mem_load_uops_retired.hit_lfb"
,
1460
},
1461
{
1462
.event_code = {0xD2},
1463
.umask = 0x01,
1464
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_miss"
,
1465
},
1466
{
1467
.event_code = {0xD2},
1468
.umask = 0x02,
1469
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_hit"
,
1470
},
1471
{
1472
.event_code = {0xD2},
1473
.umask = 0x04,
1474
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_hitm"
,
1475
},
1476
{
1477
.event_code = {0xD2},
1478
.umask = 0x08,
1479
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_none"
,
1480
},
1481
{
1482
.event_code = {0xD3},
1483
.umask = 0x01,
1484
.event_name =
"mem_load_uops_l3_miss_retired.local_dram"
,
1485
},
1486
{
1487
.event_code = {0xe6},
1488
.umask = 0x1f,
1489
.event_name =
"baclears.any"
,
1490
},
1491
{
1492
.event_code = {0xF0},
1493
.umask = 0x01,
1494
.event_name =
"l2_trans.demand_data_rd"
,
1495
},
1496
{
1497
.event_code = {0xF0},
1498
.umask = 0x02,
1499
.event_name =
"l2_trans.rfo"
,
1500
},
1501
{
1502
.event_code = {0xF0},
1503
.umask = 0x04,
1504
.event_name =
"l2_trans.code_rd"
,
1505
},
1506
{
1507
.event_code = {0xF0},
1508
.umask = 0x08,
1509
.event_name =
"l2_trans.all_pf"
,
1510
},
1511
{
1512
.event_code = {0xF0},
1513
.umask = 0x10,
1514
.event_name =
"l2_trans.l1d_wb"
,
1515
},
1516
{
1517
.event_code = {0xF0},
1518
.umask = 0x20,
1519
.event_name =
"l2_trans.l2_fill"
,
1520
},
1521
{
1522
.event_code = {0xF0},
1523
.umask = 0x40,
1524
.event_name =
"l2_trans.l2_wb"
,
1525
},
1526
{
1527
.event_code = {0xF0},
1528
.umask = 0x80,
1529
.event_name =
"l2_trans.all_requests"
,
1530
},
1531
{
1532
.event_code = {0xF1},
1533
.umask = 0x01,
1534
.event_name =
"l2_lines_in.i"
,
1535
},
1536
{
1537
.event_code = {0xF1},
1538
.umask = 0x02,
1539
.event_name =
"l2_lines_in.s"
,
1540
},
1541
{
1542
.event_code = {0xF1},
1543
.umask = 0x04,
1544
.event_name =
"l2_lines_in.e"
,
1545
},
1546
{
1547
.event_code = {0xF1},
1548
.umask = 0x07,
1549
.event_name =
"l2_lines_in.all"
,
1550
},
1551
{
1552
.event_code = {0xF2},
1553
.umask = 0x05,
1554
.event_name =
"l2_lines_out.demand_clean"
,
1555
},
1556
{
1557
.event_code = {0xf4},
1558
.umask = 0x10,
1559
.event_name =
"sq_misc.split_lock"
,
1560
},
1561
{
1562
.event_name = 0,
1563
},
1564
};
1565
1566
PERFMON_REGISTER_INTEL_PMC
(
cpu_model_table
,
event_table
);
1567
event_table
static perfmon_intel_pmc_event_t event_table[]
Definition:
perfmon_intel_bdw.c:10
perfmon_intel_pmc_event_t::event_code
u8 event_code[2]
Definition:
perfmon_intel.h:26
perfmon_intel_pmc_event_t
Definition:
perfmon_intel.h:24
PERFMON_REGISTER_INTEL_PMC
PERFMON_REGISTER_INTEL_PMC(cpu_model_table, event_table)
cpu_model_table
static perfmon_intel_pmc_cpu_model_t cpu_model_table[]
Definition:
perfmon_intel_bdw.c:4
perfmon_intel_pmc_cpu_model_t
Definition:
perfmon_intel.h:35
perfmon_intel.h
extras
deprecated
perfmon
perfmon_intel_bdw.c
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