FD.io VPP
v21.10.1-2-g0a485f517
Vector Packet Processing
perfmon_intel_hsx.c
Go to the documentation of this file.
1
2
#include <
perfmon/perfmon_intel.h
>
3
4
static
perfmon_intel_pmc_cpu_model_t
cpu_model_table
[] = {
5
{0x3F, 0x00, 0},
6
7
};
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static
perfmon_intel_pmc_event_t
event_table
[] = {
10
{
11
.
event_code
= {0x00},
12
.umask = 0x01,
13
.event_name =
"inst_retired.any"
,
14
},
15
{
16
.event_code = {0x00},
17
.umask = 0x02,
18
.event_name =
"cpu_clk_unhalted.thread"
,
19
},
20
{
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.event_code = {0x00},
22
.umask = 0x02,
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.event_name =
"cpu_clk_unhalted.thread_any"
,
24
},
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{
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.event_code = {0x00},
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.umask = 0x03,
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.event_name =
"cpu_clk_unhalted.ref_tsc"
,
29
},
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{
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.event_code = {0x03},
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.umask = 0x02,
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.event_name =
"ld_blocks.store_forward"
,
34
},
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{
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.event_code = {0x03},
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.umask = 0x08,
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.event_name =
"ld_blocks.no_sr"
,
39
},
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{
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.event_code = {0x05},
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.umask = 0x01,
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.event_name =
"misalign_mem_ref.loads"
,
44
},
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{
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.event_code = {0x05},
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.umask = 0x02,
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.event_name =
"misalign_mem_ref.stores"
,
49
},
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{
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.event_code = {0x07},
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.umask = 0x01,
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.event_name =
"ld_blocks_partial.address_alias"
,
54
},
55
{
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.event_code = {0x08},
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.umask = 0x01,
58
.event_name =
"dtlb_load_misses.miss_causes_a_walk"
,
59
},
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{
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.event_code = {0x08},
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.umask = 0x02,
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.event_name =
"dtlb_load_misses.walk_completed_4k"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x04,
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.event_name =
"dtlb_load_misses.walk_completed_2m_4m"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x08,
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.event_name =
"dtlb_load_misses.walk_completed_1g"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x0e,
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.event_name =
"dtlb_load_misses.walk_completed"
,
79
},
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{
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.event_code = {0x08},
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.umask = 0x10,
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.event_name =
"dtlb_load_misses.walk_duration"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x20,
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.event_name =
"dtlb_load_misses.stlb_hit_4k"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x40,
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.event_name =
"dtlb_load_misses.stlb_hit_2m"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x60,
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.event_name =
"dtlb_load_misses.stlb_hit"
,
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},
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{
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.event_code = {0x08},
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.umask = 0x80,
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.event_name =
"dtlb_load_misses.pde_cache_miss"
,
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},
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{
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.event_code = {0x0D},
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.umask = 0x03,
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.event_name =
"int_misc.recovery_cycles"
,
109
},
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{
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.event_code = {0x0D},
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.umask = 0x03,
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.event_name =
"int_misc.recovery_cycles_any"
,
114
},
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{
116
.event_code = {0x0E},
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.umask = 0x01,
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.event_name =
"uops_issued.any"
,
119
},
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{
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.event_code = {0x0E},
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.umask = 0x01,
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.event_name =
"uops_issued.stall_cycles"
,
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},
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{
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.event_code = {0x0E},
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.umask = 0x01,
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.event_name =
"uops_issued.core_stall_cycles"
,
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},
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{
131
.event_code = {0x0E},
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.umask = 0x10,
133
.event_name =
"uops_issued.flags_merge"
,
134
},
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{
136
.event_code = {0x0E},
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.umask = 0x20,
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.event_name =
"uops_issued.slow_lea"
,
139
},
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{
141
.event_code = {0x0E},
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.umask = 0x40,
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.event_name =
"uops_issued.single_mul"
,
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},
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{
146
.event_code = {0x14},
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.umask = 0x02,
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.event_name =
"arith.divider_uops"
,
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},
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{
151
.event_code = {0x24},
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.umask = 0x21,
153
.event_name =
"l2_rqsts.demand_data_rd_miss"
,
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},
155
{
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.event_code = {0x24},
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.umask = 0x22,
158
.event_name =
"l2_rqsts.rfo_miss"
,
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},
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{
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.event_code = {0x24},
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.umask = 0x24,
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.event_name =
"l2_rqsts.code_rd_miss"
,
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},
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{
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.event_code = {0x24},
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.umask = 0x27,
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.event_name =
"l2_rqsts.all_demand_miss"
,
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},
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{
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.event_code = {0x24},
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.umask = 0x30,
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.event_name =
"l2_rqsts.l2_pf_miss"
,
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},
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{
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.event_code = {0x24},
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.umask = 0x3F,
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.event_name =
"l2_rqsts.miss"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xc1,
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.event_name =
"l2_rqsts.demand_data_rd_hit"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xc2,
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.event_name =
"l2_rqsts.rfo_hit"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xc4,
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.event_name =
"l2_rqsts.code_rd_hit"
,
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},
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{
196
.event_code = {0x24},
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.umask = 0xd0,
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.event_name =
"l2_rqsts.l2_pf_hit"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xE1,
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.event_name =
"l2_rqsts.all_demand_data_rd"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xE2,
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.event_name =
"l2_rqsts.all_rfo"
,
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},
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{
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.event_code = {0x24},
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.umask = 0xE4,
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.event_name =
"l2_rqsts.all_code_rd"
,
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},
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{
216
.event_code = {0x24},
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.umask = 0xe7,
218
.event_name =
"l2_rqsts.all_demand_references"
,
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},
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{
221
.event_code = {0x24},
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.umask = 0xF8,
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.event_name =
"l2_rqsts.all_pf"
,
224
},
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{
226
.event_code = {0x24},
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.umask = 0xFF,
228
.event_name =
"l2_rqsts.references"
,
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},
230
{
231
.event_code = {0x27},
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.umask = 0x50,
233
.event_name =
"l2_demand_rqsts.wb_hit"
,
234
},
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{
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.event_code = {0x2E},
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.umask = 0x41,
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.event_name =
"longest_lat_cache.miss"
,
239
},
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{
241
.event_code = {0x2E},
242
.umask = 0x4F,
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.event_name =
"longest_lat_cache.reference"
,
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},
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{
246
.event_code = {0x3C},
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.umask = 0x00,
248
.event_name =
"cpu_clk_unhalted.thread_p"
,
249
},
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{
251
.event_code = {0x3C},
252
.umask = 0x00,
253
.event_name =
"cpu_clk_unhalted.thread_p_any"
,
254
},
255
{
256
.event_code = {0x3C},
257
.umask = 0x01,
258
.event_name =
"cpu_clk_thread_unhalted.ref_xclk"
,
259
},
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{
261
.event_code = {0x3C},
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.umask = 0x01,
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.event_name =
"cpu_clk_thread_unhalted.ref_xclk_any"
,
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},
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{
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.event_code = {0x3c},
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.umask = 0x02,
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.event_name =
"cpu_clk_thread_unhalted.one_thread_active"
,
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},
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{
271
.event_code = {0x48},
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.umask = 0x01,
273
.event_name =
"l1d_pend_miss.pending"
,
274
},
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{
276
.event_code = {0x48},
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.umask = 0x01,
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.event_name =
"l1d_pend_miss.pending_cycles"
,
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},
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{
281
.event_code = {0x48},
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.umask = 0x02,
283
.event_name =
"l1d_pend_miss.request_fb_full"
,
284
},
285
{
286
.event_code = {0x49},
287
.umask = 0x01,
288
.event_name =
"dtlb_store_misses.miss_causes_a_walk"
,
289
},
290
{
291
.event_code = {0x49},
292
.umask = 0x02,
293
.event_name =
"dtlb_store_misses.walk_completed_4k"
,
294
},
295
{
296
.event_code = {0x49},
297
.umask = 0x04,
298
.event_name =
"dtlb_store_misses.walk_completed_2m_4m"
,
299
},
300
{
301
.event_code = {0x49},
302
.umask = 0x08,
303
.event_name =
"dtlb_store_misses.walk_completed_1g"
,
304
},
305
{
306
.event_code = {0x49},
307
.umask = 0x0e,
308
.event_name =
"dtlb_store_misses.walk_completed"
,
309
},
310
{
311
.event_code = {0x49},
312
.umask = 0x10,
313
.event_name =
"dtlb_store_misses.walk_duration"
,
314
},
315
{
316
.event_code = {0x49},
317
.umask = 0x20,
318
.event_name =
"dtlb_store_misses.stlb_hit_4k"
,
319
},
320
{
321
.event_code = {0x49},
322
.umask = 0x40,
323
.event_name =
"dtlb_store_misses.stlb_hit_2m"
,
324
},
325
{
326
.event_code = {0x49},
327
.umask = 0x60,
328
.event_name =
"dtlb_store_misses.stlb_hit"
,
329
},
330
{
331
.event_code = {0x49},
332
.umask = 0x80,
333
.event_name =
"dtlb_store_misses.pde_cache_miss"
,
334
},
335
{
336
.event_code = {0x4c},
337
.umask = 0x01,
338
.event_name =
"load_hit_pre.sw_pf"
,
339
},
340
{
341
.event_code = {0x4c},
342
.umask = 0x02,
343
.event_name =
"load_hit_pre.hw_pf"
,
344
},
345
{
346
.event_code = {0x4f},
347
.umask = 0x10,
348
.event_name =
"ept.walk_cycles"
,
349
},
350
{
351
.event_code = {0x51},
352
.umask = 0x01,
353
.event_name =
"l1d.replacement"
,
354
},
355
{
356
.event_code = {0x54},
357
.umask = 0x01,
358
.event_name =
"tx_mem.abort_conflict"
,
359
},
360
{
361
.event_code = {0x54},
362
.umask = 0x02,
363
.event_name =
"tx_mem.abort_capacity_write"
,
364
},
365
{
366
.event_code = {0x54},
367
.umask = 0x04,
368
.event_name =
"tx_mem.abort_hle_store_to_elided_lock"
,
369
},
370
{
371
.event_code = {0x54},
372
.umask = 0x08,
373
.event_name =
"tx_mem.abort_hle_elision_buffer_not_empty"
,
374
},
375
{
376
.event_code = {0x54},
377
.umask = 0x10,
378
.event_name =
"tx_mem.abort_hle_elision_buffer_mismatch"
,
379
},
380
{
381
.event_code = {0x54},
382
.umask = 0x20,
383
.event_name =
"tx_mem.abort_hle_elision_buffer_unsupported_alignment"
,
384
},
385
{
386
.event_code = {0x54},
387
.umask = 0x40,
388
.event_name =
"tx_mem.hle_elision_buffer_full"
,
389
},
390
{
391
.event_code = {0x58},
392
.umask = 0x01,
393
.event_name =
"move_elimination.int_eliminated"
,
394
},
395
{
396
.event_code = {0x58},
397
.umask = 0x02,
398
.event_name =
"move_elimination.simd_eliminated"
,
399
},
400
{
401
.event_code = {0x58},
402
.umask = 0x04,
403
.event_name =
"move_elimination.int_not_eliminated"
,
404
},
405
{
406
.event_code = {0x58},
407
.umask = 0x08,
408
.event_name =
"move_elimination.simd_not_eliminated"
,
409
},
410
{
411
.event_code = {0x5C},
412
.umask = 0x01,
413
.event_name =
"cpl_cycles.ring0"
,
414
},
415
{
416
.event_code = {0x5C},
417
.umask = 0x01,
418
.event_name =
"cpl_cycles.ring0_trans"
,
419
},
420
{
421
.event_code = {0x5C},
422
.umask = 0x02,
423
.event_name =
"cpl_cycles.ring123"
,
424
},
425
{
426
.event_code = {0x5d},
427
.umask = 0x01,
428
.event_name =
"tx_exec.misc1"
,
429
},
430
{
431
.event_code = {0x5d},
432
.umask = 0x02,
433
.event_name =
"tx_exec.misc2"
,
434
},
435
{
436
.event_code = {0x5d},
437
.umask = 0x04,
438
.event_name =
"tx_exec.misc3"
,
439
},
440
{
441
.event_code = {0x5d},
442
.umask = 0x08,
443
.event_name =
"tx_exec.misc4"
,
444
},
445
{
446
.event_code = {0x5d},
447
.umask = 0x10,
448
.event_name =
"tx_exec.misc5"
,
449
},
450
{
451
.event_code = {0x5E},
452
.umask = 0x01,
453
.event_name =
"rs_events.empty_cycles"
,
454
},
455
{
456
.event_code = {0x5E},
457
.umask = 0x01,
458
.event_name =
"rs_events.empty_end"
,
459
},
460
{
461
.event_code = {0x60},
462
.umask = 0x01,
463
.event_name =
"offcore_requests_outstanding.demand_data_rd"
,
464
},
465
{
466
.event_code = {0x60},
467
.umask = 0x01,
468
.event_name =
"offcore_requests_outstanding.cycles_with_demand_data_rd"
,
469
},
470
{
471
.event_code = {0x60},
472
.umask = 0x02,
473
.event_name =
"offcore_requests_outstanding.demand_code_rd"
,
474
},
475
{
476
.event_code = {0x60},
477
.umask = 0x04,
478
.event_name =
"offcore_requests_outstanding.demand_rfo"
,
479
},
480
{
481
.event_code = {0x60},
482
.umask = 0x04,
483
.event_name =
"offcore_requests_outstanding.cycles_with_demand_rfo"
,
484
},
485
{
486
.event_code = {0x60},
487
.umask = 0x08,
488
.event_name =
"offcore_requests_outstanding.all_data_rd"
,
489
},
490
{
491
.event_code = {0x60},
492
.umask = 0x08,
493
.event_name =
"offcore_requests_outstanding.cycles_with_data_rd"
,
494
},
495
{
496
.event_code = {0x63},
497
.umask = 0x01,
498
.event_name =
"lock_cycles.split_lock_uc_lock_duration"
,
499
},
500
{
501
.event_code = {0x63},
502
.umask = 0x02,
503
.event_name =
"lock_cycles.cache_lock_duration"
,
504
},
505
{
506
.event_code = {0x79},
507
.umask = 0x02,
508
.event_name =
"idq.empty"
,
509
},
510
{
511
.event_code = {0x79},
512
.umask = 0x04,
513
.event_name =
"idq.mite_uops"
,
514
},
515
{
516
.event_code = {0x79},
517
.umask = 0x04,
518
.event_name =
"idq.mite_cycles"
,
519
},
520
{
521
.event_code = {0x79},
522
.umask = 0x08,
523
.event_name =
"idq.dsb_uops"
,
524
},
525
{
526
.event_code = {0x79},
527
.umask = 0x08,
528
.event_name =
"idq.dsb_cycles"
,
529
},
530
{
531
.event_code = {0x79},
532
.umask = 0x10,
533
.event_name =
"idq.ms_dsb_uops"
,
534
},
535
{
536
.event_code = {0x79},
537
.umask = 0x10,
538
.event_name =
"idq.ms_dsb_cycles"
,
539
},
540
{
541
.event_code = {0x79},
542
.umask = 0x10,
543
.event_name =
"idq.ms_dsb_occur"
,
544
},
545
{
546
.event_code = {0x79},
547
.umask = 0x18,
548
.event_name =
"idq.all_dsb_cycles_4_uops"
,
549
},
550
{
551
.event_code = {0x79},
552
.umask = 0x18,
553
.event_name =
"idq.all_dsb_cycles_any_uops"
,
554
},
555
{
556
.event_code = {0x79},
557
.umask = 0x20,
558
.event_name =
"idq.ms_mite_uops"
,
559
},
560
{
561
.event_code = {0x79},
562
.umask = 0x24,
563
.event_name =
"idq.all_mite_cycles_4_uops"
,
564
},
565
{
566
.event_code = {0x79},
567
.umask = 0x24,
568
.event_name =
"idq.all_mite_cycles_any_uops"
,
569
},
570
{
571
.event_code = {0x79},
572
.umask = 0x30,
573
.event_name =
"idq.ms_uops"
,
574
},
575
{
576
.event_code = {0x79},
577
.umask = 0x30,
578
.event_name =
"idq.ms_cycles"
,
579
},
580
{
581
.event_code = {0x79},
582
.umask = 0x30,
583
.event_name =
"idq.ms_switches"
,
584
},
585
{
586
.event_code = {0x79},
587
.umask = 0x3c,
588
.event_name =
"idq.mite_all_uops"
,
589
},
590
{
591
.event_code = {0x80},
592
.umask = 0x01,
593
.event_name =
"icache.hit"
,
594
},
595
{
596
.event_code = {0x80},
597
.umask = 0x02,
598
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{
1171
.event_code = {0xC1},
1172
.umask = 0x40,
1173
.event_name =
"other_assists.any_wb_assist"
,
1174
},
1175
{
1176
.event_code = {0xC2},
1177
.umask = 0x01,
1178
.event_name =
"uops_retired.all"
,
1179
},
1180
{
1181
.event_code = {0xC2},
1182
.umask = 0x01,
1183
.event_name =
"uops_retired.stall_cycles"
,
1184
},
1185
{
1186
.event_code = {0xC2},
1187
.umask = 0x01,
1188
.event_name =
"uops_retired.total_cycles"
,
1189
},
1190
{
1191
.event_code = {0xC2},
1192
.umask = 0x01,
1193
.event_name =
"uops_retired.core_stall_cycles"
,
1194
},
1195
{
1196
.event_code = {0xC2},
1197
.umask = 0x02,
1198
.event_name =
"uops_retired.retire_slots"
,
1199
},
1200
{
1201
.event_code = {0xC3},
1202
.umask = 0x01,
1203
.event_name =
"machine_clears.cycles"
,
1204
},
1205
{
1206
.event_code = {0xC3},
1207
.umask = 0x01,
1208
.event_name =
"machine_clears.count"
,
1209
},
1210
{
1211
.event_code = {0xC3},
1212
.umask = 0x02,
1213
.event_name =
"machine_clears.memory_ordering"
,
1214
},
1215
{
1216
.event_code = {0xC3},
1217
.umask = 0x04,
1218
.event_name =
"machine_clears.smc"
,
1219
},
1220
{
1221
.event_code = {0xC3},
1222
.umask = 0x20,
1223
.event_name =
"machine_clears.maskmov"
,
1224
},
1225
{
1226
.event_code = {0xC4},
1227
.umask = 0x00,
1228
.event_name =
"br_inst_retired.all_branches"
,
1229
},
1230
{
1231
.event_code = {0xC4},
1232
.umask = 0x01,
1233
.event_name =
"br_inst_retired.conditional"
,
1234
},
1235
{
1236
.event_code = {0xC4},
1237
.umask = 0x02,
1238
.event_name =
"br_inst_retired.near_call"
,
1239
},
1240
{
1241
.event_code = {0xC4},
1242
.umask = 0x02,
1243
.event_name =
"br_inst_retired.near_call_r3"
,
1244
},
1245
{
1246
.event_code = {0xC4},
1247
.umask = 0x04,
1248
.event_name =
"br_inst_retired.all_branches_pebs"
,
1249
},
1250
{
1251
.event_code = {0xC4},
1252
.umask = 0x08,
1253
.event_name =
"br_inst_retired.near_return"
,
1254
},
1255
{
1256
.event_code = {0xC4},
1257
.umask = 0x10,
1258
.event_name =
"br_inst_retired.not_taken"
,
1259
},
1260
{
1261
.event_code = {0xC4},
1262
.umask = 0x20,
1263
.event_name =
"br_inst_retired.near_taken"
,
1264
},
1265
{
1266
.event_code = {0xC4},
1267
.umask = 0x40,
1268
.event_name =
"br_inst_retired.far_branch"
,
1269
},
1270
{
1271
.event_code = {0xC5},
1272
.umask = 0x00,
1273
.event_name =
"br_misp_retired.all_branches"
,
1274
},
1275
{
1276
.event_code = {0xC5},
1277
.umask = 0x01,
1278
.event_name =
"br_misp_retired.conditional"
,
1279
},
1280
{
1281
.event_code = {0xC5},
1282
.umask = 0x04,
1283
.event_name =
"br_misp_retired.all_branches_pebs"
,
1284
},
1285
{
1286
.event_code = {0xC5},
1287
.umask = 0x20,
1288
.event_name =
"br_misp_retired.near_taken"
,
1289
},
1290
{
1291
.event_code = {0xC6},
1292
.umask = 0x07,
1293
.event_name =
"avx_insts.all"
,
1294
},
1295
{
1296
.event_code = {0xC8},
1297
.umask = 0x01,
1298
.event_name =
"hle_retired.start"
,
1299
},
1300
{
1301
.event_code = {0xc8},
1302
.umask = 0x02,
1303
.event_name =
"hle_retired.commit"
,
1304
},
1305
{
1306
.event_code = {0xc8},
1307
.umask = 0x04,
1308
.event_name =
"hle_retired.aborted"
,
1309
},
1310
{
1311
.event_code = {0xc8},
1312
.umask = 0x08,
1313
.event_name =
"hle_retired.aborted_misc1"
,
1314
},
1315
{
1316
.event_code = {0xc8},
1317
.umask = 0x10,
1318
.event_name =
"hle_retired.aborted_misc2"
,
1319
},
1320
{
1321
.event_code = {0xc8},
1322
.umask = 0x20,
1323
.event_name =
"hle_retired.aborted_misc3"
,
1324
},
1325
{
1326
.event_code = {0xc8},
1327
.umask = 0x40,
1328
.event_name =
"hle_retired.aborted_misc4"
,
1329
},
1330
{
1331
.event_code = {0xc8},
1332
.umask = 0x80,
1333
.event_name =
"hle_retired.aborted_misc5"
,
1334
},
1335
{
1336
.event_code = {0xC9},
1337
.umask = 0x01,
1338
.event_name =
"rtm_retired.start"
,
1339
},
1340
{
1341
.event_code = {0xc9},
1342
.umask = 0x02,
1343
.event_name =
"rtm_retired.commit"
,
1344
},
1345
{
1346
.event_code = {0xc9},
1347
.umask = 0x04,
1348
.event_name =
"rtm_retired.aborted"
,
1349
},
1350
{
1351
.event_code = {0xc9},
1352
.umask = 0x08,
1353
.event_name =
"rtm_retired.aborted_misc1"
,
1354
},
1355
{
1356
.event_code = {0xc9},
1357
.umask = 0x10,
1358
.event_name =
"rtm_retired.aborted_misc2"
,
1359
},
1360
{
1361
.event_code = {0xc9},
1362
.umask = 0x20,
1363
.event_name =
"rtm_retired.aborted_misc3"
,
1364
},
1365
{
1366
.event_code = {0xc9},
1367
.umask = 0x40,
1368
.event_name =
"rtm_retired.aborted_misc4"
,
1369
},
1370
{
1371
.event_code = {0xc9},
1372
.umask = 0x80,
1373
.event_name =
"rtm_retired.aborted_misc5"
,
1374
},
1375
{
1376
.event_code = {0xCA},
1377
.umask = 0x02,
1378
.event_name =
"fp_assist.x87_output"
,
1379
},
1380
{
1381
.event_code = {0xCA},
1382
.umask = 0x04,
1383
.event_name =
"fp_assist.x87_input"
,
1384
},
1385
{
1386
.event_code = {0xCA},
1387
.umask = 0x08,
1388
.event_name =
"fp_assist.simd_output"
,
1389
},
1390
{
1391
.event_code = {0xCA},
1392
.umask = 0x10,
1393
.event_name =
"fp_assist.simd_input"
,
1394
},
1395
{
1396
.event_code = {0xCA},
1397
.umask = 0x1E,
1398
.event_name =
"fp_assist.any"
,
1399
},
1400
{
1401
.event_code = {0xCC},
1402
.umask = 0x20,
1403
.event_name =
"rob_misc_events.lbr_inserts"
,
1404
},
1405
{
1406
.event_code = {0xD0},
1407
.umask = 0x11,
1408
.event_name =
"mem_uops_retired.stlb_miss_loads"
,
1409
},
1410
{
1411
.event_code = {0xD0},
1412
.umask = 0x12,
1413
.event_name =
"mem_uops_retired.stlb_miss_stores"
,
1414
},
1415
{
1416
.event_code = {0xD0},
1417
.umask = 0x21,
1418
.event_name =
"mem_uops_retired.lock_loads"
,
1419
},
1420
{
1421
.event_code = {0xD0},
1422
.umask = 0x41,
1423
.event_name =
"mem_uops_retired.split_loads"
,
1424
},
1425
{
1426
.event_code = {0xD0},
1427
.umask = 0x42,
1428
.event_name =
"mem_uops_retired.split_stores"
,
1429
},
1430
{
1431
.event_code = {0xD0},
1432
.umask = 0x81,
1433
.event_name =
"mem_uops_retired.all_loads"
,
1434
},
1435
{
1436
.event_code = {0xD0},
1437
.umask = 0x82,
1438
.event_name =
"mem_uops_retired.all_stores"
,
1439
},
1440
{
1441
.event_code = {0xD1},
1442
.umask = 0x01,
1443
.event_name =
"mem_load_uops_retired.l1_hit"
,
1444
},
1445
{
1446
.event_code = {0xD1},
1447
.umask = 0x02,
1448
.event_name =
"mem_load_uops_retired.l2_hit"
,
1449
},
1450
{
1451
.event_code = {0xD1},
1452
.umask = 0x04,
1453
.event_name =
"mem_load_uops_retired.l3_hit"
,
1454
},
1455
{
1456
.event_code = {0xD1},
1457
.umask = 0x08,
1458
.event_name =
"mem_load_uops_retired.l1_miss"
,
1459
},
1460
{
1461
.event_code = {0xD1},
1462
.umask = 0x10,
1463
.event_name =
"mem_load_uops_retired.l2_miss"
,
1464
},
1465
{
1466
.event_code = {0xD1},
1467
.umask = 0x20,
1468
.event_name =
"mem_load_uops_retired.l3_miss"
,
1469
},
1470
{
1471
.event_code = {0xD1},
1472
.umask = 0x40,
1473
.event_name =
"mem_load_uops_retired.hit_lfb"
,
1474
},
1475
{
1476
.event_code = {0xD2},
1477
.umask = 0x01,
1478
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_miss"
,
1479
},
1480
{
1481
.event_code = {0xD2},
1482
.umask = 0x02,
1483
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_hit"
,
1484
},
1485
{
1486
.event_code = {0xD2},
1487
.umask = 0x04,
1488
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_hitm"
,
1489
},
1490
{
1491
.event_code = {0xD2},
1492
.umask = 0x08,
1493
.event_name =
"mem_load_uops_l3_hit_retired.xsnp_none"
,
1494
},
1495
{
1496
.event_code = {0xD3},
1497
.umask = 0x01,
1498
.event_name =
"mem_load_uops_l3_miss_retired.local_dram"
,
1499
},
1500
{
1501
.event_code = {0xD3},
1502
.umask = 0x04,
1503
.event_name =
"mem_load_uops_l3_miss_retired.remote_dram"
,
1504
},
1505
{
1506
.event_code = {0xD3},
1507
.umask = 0x10,
1508
.event_name =
"mem_load_uops_l3_miss_retired.remote_hitm"
,
1509
},
1510
{
1511
.event_code = {0xD3},
1512
.umask = 0x20,
1513
.event_name =
"mem_load_uops_l3_miss_retired.remote_fwd"
,
1514
},
1515
{
1516
.event_code = {0xe6},
1517
.umask = 0x1f,
1518
.event_name =
"baclears.any"
,
1519
},
1520
{
1521
.event_code = {0xf0},
1522
.umask = 0x01,
1523
.event_name =
"l2_trans.demand_data_rd"
,
1524
},
1525
{
1526
.event_code = {0xf0},
1527
.umask = 0x02,
1528
.event_name =
"l2_trans.rfo"
,
1529
},
1530
{
1531
.event_code = {0xf0},
1532
.umask = 0x04,
1533
.event_name =
"l2_trans.code_rd"
,
1534
},
1535
{
1536
.event_code = {0xf0},
1537
.umask = 0x08,
1538
.event_name =
"l2_trans.all_pf"
,
1539
},
1540
{
1541
.event_code = {0xf0},
1542
.umask = 0x10,
1543
.event_name =
"l2_trans.l1d_wb"
,
1544
},
1545
{
1546
.event_code = {0xf0},
1547
.umask = 0x20,
1548
.event_name =
"l2_trans.l2_fill"
,
1549
},
1550
{
1551
.event_code = {0xf0},
1552
.umask = 0x40,
1553
.event_name =
"l2_trans.l2_wb"
,
1554
},
1555
{
1556
.event_code = {0xf0},
1557
.umask = 0x80,
1558
.event_name =
"l2_trans.all_requests"
,
1559
},
1560
{
1561
.event_code = {0xF1},
1562
.umask = 0x01,
1563
.event_name =
"l2_lines_in.i"
,
1564
},
1565
{
1566
.event_code = {0xF1},
1567
.umask = 0x02,
1568
.event_name =
"l2_lines_in.s"
,
1569
},
1570
{
1571
.event_code = {0xF1},
1572
.umask = 0x04,
1573
.event_name =
"l2_lines_in.e"
,
1574
},
1575
{
1576
.event_code = {0xF1},
1577
.umask = 0x07,
1578
.event_name =
"l2_lines_in.all"
,
1579
},
1580
{
1581
.event_code = {0xF2},
1582
.umask = 0x05,
1583
.event_name =
"l2_lines_out.demand_clean"
,
1584
},
1585
{
1586
.event_code = {0xF2},
1587
.umask = 0x06,
1588
.event_name =
"l2_lines_out.demand_dirty"
,
1589
},
1590
{
1591
.event_code = {0xf4},
1592
.umask = 0x10,
1593
.event_name =
"sq_misc.split_lock"
,
1594
},
1595
{
1596
.event_name = 0,
1597
},
1598
};
1599
1600
PERFMON_REGISTER_INTEL_PMC
(
cpu_model_table
,
event_table
);
1601
perfmon_intel_pmc_event_t::event_code
u8 event_code[2]
Definition:
perfmon_intel.h:26
cpu_model_table
static perfmon_intel_pmc_cpu_model_t cpu_model_table[]
Definition:
perfmon_intel_hsx.c:4
perfmon_intel_pmc_event_t
Definition:
perfmon_intel.h:24
PERFMON_REGISTER_INTEL_PMC
PERFMON_REGISTER_INTEL_PMC(cpu_model_table, event_table)
event_table
static perfmon_intel_pmc_event_t event_table[]
Definition:
perfmon_intel_hsx.c:9
perfmon_intel_pmc_cpu_model_t
Definition:
perfmon_intel.h:35
perfmon_intel.h
extras
deprecated
perfmon
perfmon_intel_hsx.c
Generated on Sat Jan 8 2022 10:34:44 for FD.io VPP by
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