FD.io VPP
v17.04.2-2-ga8f93f8
Vector Packet Processing
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Data Structures | |
struct | pci_config_header_t |
struct | pci_config_type0_regs_t |
struct | pci_config_type1_regs_t |
Macros | |
#define | PCI_COMMAND_IO (1 << 0) /* Enable response in I/O space */ |
#define | PCI_COMMAND_MEMORY (1 << 1) /* Enable response in Memory space */ |
#define | PCI_COMMAND_BUS_MASTER (1 << 2) /* Enable bus mastering */ |
#define | PCI_COMMAND_SPECIAL (1 << 3) /* Enable response to special cycles */ |
#define | PCI_COMMAND_WRITE_INVALIDATE (1 << 4) /* Use memory write and invalidate */ |
#define | PCI_COMMAND_VGA_PALETTE_SNOOP (1 << 5) |
#define | PCI_COMMAND_PARITY (1 << 6) |
#define | PCI_COMMAND_WAIT (1 << 7) /* Enable address/data stepping */ |
#define | PCI_COMMAND_SERR (1 << 8) /* Enable SERR */ |
#define | PCI_COMMAND_BACK_TO_BACK_WRITE (1 << 9) |
#define | PCI_COMMAND_INTX_DISABLE (1 << 10) /* INTx Emulation Disable */ |
#define | PCI_STATUS_INTX_PENDING (1 << 3) |
#define | PCI_STATUS_CAPABILITY_LIST (1 << 4) |
#define | PCI_STATUS_66MHZ (1 << 5) /* Support 66 Mhz PCI 2.1 bus */ |
#define | PCI_STATUS_UDF (1 << 6) /* Support User Definable Features (obsolete) */ |
#define | PCI_STATUS_BACK_TO_BACK_WRITE (1 << 7) /* Accept fast-back to back */ |
#define | PCI_STATUS_PARITY_ERROR (1 << 8) /* Detected parity error */ |
#define | PCI_STATUS_DEVSEL_GET(x) ((x >> 9) & 3) /* DEVSEL timing */ |
#define | PCI_STATUS_DEVSEL_FAST (0 << 9) |
#define | PCI_STATUS_DEVSEL_MEDIUM (1 << 9) |
#define | PCI_STATUS_DEVSEL_SLOW (2 << 9) |
#define | PCI_STATUS_SIG_TARGET_ABORT (1 << 11) /* Set on target abort */ |
#define | PCI_STATUS_REC_TARGET_ABORT (1 << 12) /* Master ack of " */ |
#define | PCI_STATUS_REC_MASTER_ABORT (1 << 13) /* Set on master abort */ |
#define | PCI_STATUS_SIG_SYSTEM_ERROR (1 << 14) /* Set when we drive SERR */ |
#define | PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15) |
#define | PCI_HEADER_TYPE_NORMAL 0 |
#define | PCI_HEADER_TYPE_BRIDGE 1 |
#define | PCI_HEADER_TYPE_CARDBUS 2 |
#define | PCI_BIST_CODE_MASK 0x0f /* Return result */ |
#define | PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
#define | PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
#define | PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
#define | PCI_ROM_ADDRESS_ENABLE 0x01 |
#define | PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
#define | PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL |
#define | PCI_MEMORY_RANGE_MASK (~0x0fUL) |
#define | PCI_PREF_RANGE_TYPE_MASK 0x0fUL |
#define | PCI_PREF_RANGE_TYPE_32 0x00 |
#define | PCI_PREF_RANGE_TYPE_64 0x01 |
#define | PCI_PREF_RANGE_MASK (~0x0fUL) |
#define | PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
#define | PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
#define | PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
#define | PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
#define | PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
#define | PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
#define | PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
#define | PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
#define | PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
#define | PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ |
#define | PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
#define | PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ |
#define | PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
#define | PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
#define | PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
#define | PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ |
#define | PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ |
#define | PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ |
#define | PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ |
#define | PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ |
#define | PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ |
#define | PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
#define | PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
#define | PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ |
#define | PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |
#define | PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ |
#define | PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ |
#define | PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ |
#define | PCI_AGP_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
#define | PCI_AGP_SBA 0x0200 /* Sideband addressing supported */ |
#define | PCI_AGP_64BIT 0x0020 /* 64-bit addressing supported */ |
#define | PCI_AGP_ALLOW_TRANSACTIONS 0x0100 /* Allow processing of AGP transactions */ |
#define | PCI_AGP_FW 0x0010 /* FW transfers supported/forced */ |
#define | PCI_AGP_RATE4 0x0004 /* 4x transfer rate supported */ |
#define | PCI_AGP_RATE2 0x0002 /* 2x transfer rate supported */ |
#define | PCI_AGP_RATE1 0x0001 /* 1x transfer rate supported */ |
#define | PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ |
#define | PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ |
#define | PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ |
#define | PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ |
#define | PCI_MSI_FLAGS_ENABLE (1 << 0) /* MSI feature enabled */ |
#define | PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE(x) ((x >> 1) & 0x7) |
#define | PCI_MSI_FLAGS_MAX_QUEUE_SIZE(x) (((x) & 0x7) << 1) |
#define | PCI_MSI_FLAGS_GET_QUEUE_SIZE(x) ((x >> 4) & 0x7) |
#define | PCI_MSI_FLAGS_QUEUE_SIZE(x) (((x) & 0x7) << 4) |
#define | PCI_MSI_FLAGS_64BIT (1 << 7) /* 64-bit addresses allowed */ |
#define | PCI_MSI_FLAGS_MASKBIT (1 << 8) /* 64-bit mask bits allowed */ |
#define | PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ |
#define | PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ |
#define | PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ |
#define | PCI_CHSWP_LOO 0x08 /* LED On / Off */ |
#define | PCI_CHSWP_PI 0x30 /* Programming Interface */ |
#define | PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ |
#define | PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ |
#define | PCIX_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
#define | PCIX_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ |
#define | PCIX_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ |
#define | PCIX_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
#define | PCIX_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
#define | PCIX_STATUS_DEVFN 0x000000ff /* A copy of devfn */ |
#define | PCIX_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ |
#define | PCIX_STATUS_64BIT 0x00010000 /* 64-bit device */ |
#define | PCIX_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ |
#define | PCIX_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ |
#define | PCIX_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ |
#define | PCIX_STATUS_COMPLEX 0x00100000 /* Device Complexity */ |
#define | PCIX_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ |
#define | PCIX_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ |
#define | PCIX_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ |
#define | PCIX_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
#define | PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
#define | PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
#define | PCIE_CAP_VERSION(x) (((x) >> 0) & 0xf) |
#define | PCIE_CAP_DEVICE_TYPE(x) (((x) >> 4) & 0xf) |
#define | PCIE_DEVICE_TYPE_ENDPOINT 0 |
#define | PCIE_DEVICE_TYPE_LEGACY_ENDPOINT 1 |
#define | PCIE_DEVICE_TYPE_ROOT_PORT 4 |
#define | PCIE_DEVICE_TYPE_SWITCH_UPSTREAM 5 |
#define | PCIE_DEVICE_TYPE_SWITCH_DOWNSTREAM 6 |
#define | PCIE_DEVICE_TYPE_PCIE_TO_PCI_BRIDGE 7 |
#define | PCIE_DEVICE_TYPE_PCI_TO_PCIE_BRIDGE 8 |
#define | PCIE_DEVICE_TYPE_ROOT_COMPLEX_ENDPOINT 9 |
#define | PCIE_DEVICE_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10 |
#define | PCIE_CAP_SLOW_IMPLEMENTED (1 << 8) |
#define | PCIE_CAP_MSI_IRQ(x) (((x) >> 9) & 0x1f) |
#define | PCIE_DEVCAP_MAX_PAYLOAD(x) (128 << (((x) >> 0) & 0x7)) |
#define | PCIE_DEVCAP_PHANTOM_BITS(x) (((x) >> 3) & 0x3) |
#define | PCIE_DEVCAP_EXTENTED_TAG (1 << 5) |
#define | PCIE_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
#define | PCIE_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
#define | PCIE_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
#define | PCIE_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
#define | PCIE_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
#define | PCIE_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
#define | PCIE_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
#define | PCIE_CTRL_CERE 0x0001 /* Correctable Error Reporting En. */ |
#define | PCIE_CTRL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
#define | PCIE_CTRL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
#define | PCIE_CTRL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
#define | PCIE_CTRL_RELAX_EN 0x0010 /* Enable relaxed ordering */ |
#define | PCIE_CTRL_MAX_PAYLOAD(n) (((n) & 7) << 5) |
#define | PCIE_CTRL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ |
#define | PCIE_CTRL_PHANTOM 0x0200 /* Phantom Functions Enable */ |
#define | PCIE_CTRL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ |
#define | PCIE_CTRL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ |
#define | PCIE_CTRL_MAX_READ_REQUEST(n) (((n) & 7) << 12) |
#define | PCIE_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
#define | PCIE_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
#define | PCIE_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ |
#define | PCIE_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ |
#define | PCIE_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
#define | PCIE_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
#define | PCIE_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
#define | PCIE_ERROR_UNC_LINK_TRAINING (1 << 0) |
#define | PCIE_ERROR_UNC_DATA_LINK_PROTOCOL (1 << 4) |
#define | PCIE_ERROR_UNC_SURPRISE_DOWN (1 << 5) |
#define | PCIE_ERROR_UNC_POISONED_TLP (1 << 12) |
#define | PCIE_ERROR_UNC_FLOW_CONTROL (1 << 13) |
#define | PCIE_ERROR_UNC_COMPLETION_TIMEOUT (1 << 14) |
#define | PCIE_ERROR_UNC_COMPLETER_ABORT (1 << 15) |
#define | PCIE_ERROR_UNC_UNEXPECTED_COMPLETION (1 << 16) |
#define | PCIE_ERROR_UNC_RX_OVERFLOW (1 << 17) |
#define | PCIE_ERROR_UNC_MALFORMED_TLP (1 << 18) |
#define | PCIE_ERROR_UNC_CRC_ERROR (1 << 19) |
#define | PCIE_ERROR_UNC_UNSUPPORTED_REQUEST (1 << 20) |
#define | PCIE_ERROR_COR_RX_ERROR (1 << 0) |
#define | PCIE_ERROR_COR_BAD_TLP (1 << 6) |
#define | PCIE_ERROR_COR_BAD_DLLP (1 << 7) |
#define | PCIE_ERROR_COR_REPLAY_ROLLOVER (1 << 8) |
#define | PCIE_ERROR_COR_REPLAY_TIMER (1 << 12) |
#define | PCIE_ERROR_COR_ADVISORY (1 << 13) |
#define | PCI_VC_PORT_REG1 4 |
#define | PCI_VC_PORT_REG2 8 |
#define | PCI_VC_PORT_CTRL 12 |
#define | PCI_VC_PORT_STATUS 14 |
#define | PCI_VC_RES_CAP 16 |
#define | PCI_VC_RES_CTRL 20 |
#define | PCI_VC_RES_STATUS 26 |
#define | PCI_PWR_DSR 4 /* Data Select Register */ |
#define | PCI_PWR_DATA 8 /* Data Register */ |
#define | PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ |
#define | PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ |
#define | PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ |
#define | PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
#define | PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
#define | PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
#define | PCI_PWR_CAP 12 /* Capability */ |
#define | PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
Typedefs | |
typedef enum pci_capability_type | pci_capability_type_t |
typedef enum pcie_capability_type | pcie_capability_type_t |
#define PCI_AGP_64BIT 0x0020 /* 64-bit addressing supported */ |
#define PCI_AGP_ALLOW_TRANSACTIONS 0x0100 /* Allow processing of AGP transactions */ |
#define PCI_AGP_FW 0x0010 /* FW transfers supported/forced */ |
#define PCI_AGP_RATE1 0x0001 /* 1x transfer rate supported */ |
#define PCI_AGP_RATE2 0x0002 /* 2x transfer rate supported */ |
#define PCI_AGP_RATE4 0x0004 /* 4x transfer rate supported */ |
#define PCI_AGP_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
#define PCI_AGP_SBA 0x0200 /* Sideband addressing supported */ |
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
Definition at line 219 of file pci_config.h.
#define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
Definition at line 217 of file pci_config.h.
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
Definition at line 218 of file pci_config.h.
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
Definition at line 339 of file pci_config.h.
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
Definition at line 340 of file pci_config.h.
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
Definition at line 338 of file pci_config.h.
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
Definition at line 336 of file pci_config.h.
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
Definition at line 334 of file pci_config.h.
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
Definition at line 335 of file pci_config.h.
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
Definition at line 337 of file pci_config.h.
#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ |
#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ |
#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ |
#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ |
#define PCI_CHSWP_LOO 0x08 /* LED On / Off */ |
#define PCI_CHSWP_PI 0x30 /* Programming Interface */ |
#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ |
#define PCI_COMMAND_BACK_TO_BACK_WRITE (1 << 9) |
Definition at line 183 of file pci_config.h.
#define PCI_COMMAND_BUS_MASTER (1 << 2) /* Enable bus mastering */ |
Definition at line 176 of file pci_config.h.
#define PCI_COMMAND_INTX_DISABLE (1 << 10) /* INTx Emulation Disable */ |
Definition at line 184 of file pci_config.h.
#define PCI_COMMAND_IO (1 << 0) /* Enable response in I/O space */ |
Definition at line 174 of file pci_config.h.
#define PCI_COMMAND_MEMORY (1 << 1) /* Enable response in Memory space */ |
Definition at line 175 of file pci_config.h.
#define PCI_COMMAND_PARITY (1 << 6) |
Definition at line 180 of file pci_config.h.
#define PCI_COMMAND_SERR (1 << 8) /* Enable SERR */ |
Definition at line 182 of file pci_config.h.
#define PCI_COMMAND_SPECIAL (1 << 3) /* Enable response to special cycles */ |
Definition at line 177 of file pci_config.h.
#define PCI_COMMAND_VGA_PALETTE_SNOOP (1 << 5) |
Definition at line 179 of file pci_config.h.
#define PCI_COMMAND_WAIT (1 << 7) /* Enable address/data stepping */ |
Definition at line 181 of file pci_config.h.
#define PCI_COMMAND_WRITE_INVALIDATE (1 << 4) /* Use memory write and invalidate */ |
Definition at line 178 of file pci_config.h.
#define PCI_HEADER_TYPE_BRIDGE 1 |
Definition at line 213 of file pci_config.h.
#define PCI_HEADER_TYPE_CARDBUS 2 |
Definition at line 214 of file pci_config.h.
#define PCI_HEADER_TYPE_NORMAL 0 |
Definition at line 212 of file pci_config.h.
#define PCI_MEMORY_RANGE_MASK (~0x0fUL) |
Definition at line 313 of file pci_config.h.
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL |
Definition at line 312 of file pci_config.h.
#define PCI_MSI_FLAGS_64BIT (1 << 7) /* 64-bit addresses allowed */ |
#define PCI_MSI_FLAGS_ENABLE (1 << 0) /* MSI feature enabled */ |
#define PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE | ( | x | ) | ((x >> 1) & 0x7) |
#define PCI_MSI_FLAGS_GET_QUEUE_SIZE | ( | x | ) | ((x >> 4) & 0x7) |
#define PCI_MSI_FLAGS_MASKBIT (1 << 8) /* 64-bit mask bits allowed */ |
#define PCI_MSI_FLAGS_MAX_QUEUE_SIZE | ( | x | ) | (((x) & 0x7) << 1) |
#define PCI_MSI_FLAGS_QUEUE_SIZE | ( | x | ) | (((x) & 0x7) << 4) |
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ |
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ |
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ |
#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ |
#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ |
#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ |
#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ |
#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ |
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ |
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ |
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ |
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ |
#define PCI_PREF_RANGE_MASK (~0x0fUL) |
Definition at line 319 of file pci_config.h.
#define PCI_PREF_RANGE_TYPE_32 0x00 |
Definition at line 317 of file pci_config.h.
#define PCI_PREF_RANGE_TYPE_64 0x01 |
Definition at line 318 of file pci_config.h.
#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL |
Definition at line 316 of file pci_config.h.
#define PCI_PWR_CAP 12 /* Capability */ |
Definition at line 720 of file pci_config.h.
#define PCI_PWR_CAP_BUDGET | ( | x | ) | ((x) & 1) /* Included in system budget */ |
Definition at line 721 of file pci_config.h.
#define PCI_PWR_DATA 8 /* Data Register */ |
Definition at line 713 of file pci_config.h.
#define PCI_PWR_DATA_BASE | ( | x | ) | ((x) & 0xff) /* Base Power */ |
Definition at line 714 of file pci_config.h.
#define PCI_PWR_DATA_PM_STATE | ( | x | ) | (((x) >> 13) & 3) /* PM State */ |
Definition at line 717 of file pci_config.h.
#define PCI_PWR_DATA_PM_SUB | ( | x | ) | (((x) >> 10) & 7) /* PM Sub State */ |
Definition at line 716 of file pci_config.h.
#define PCI_PWR_DATA_RAIL | ( | x | ) | (((x) >> 18) & 7) /* Power Rail */ |
Definition at line 719 of file pci_config.h.
#define PCI_PWR_DATA_SCALE | ( | x | ) | (((x) >> 8) & 3) /* Data Scale */ |
Definition at line 715 of file pci_config.h.
#define PCI_PWR_DATA_TYPE | ( | x | ) | (((x) >> 15) & 7) /* Type */ |
Definition at line 718 of file pci_config.h.
#define PCI_PWR_DSR 4 /* Data Select Register */ |
Definition at line 712 of file pci_config.h.
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
Definition at line 256 of file pci_config.h.
#define PCI_ROM_ADDRESS_ENABLE 0x01 |
Definition at line 257 of file pci_config.h.
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
Definition at line 258 of file pci_config.h.
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ |
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ |
#define PCI_STATUS_66MHZ (1 << 5) /* Support 66 Mhz PCI 2.1 bus */ |
Definition at line 189 of file pci_config.h.
#define PCI_STATUS_BACK_TO_BACK_WRITE (1 << 7) /* Accept fast-back to back */ |
Definition at line 191 of file pci_config.h.
#define PCI_STATUS_CAPABILITY_LIST (1 << 4) |
Definition at line 188 of file pci_config.h.
#define PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15) |
Definition at line 201 of file pci_config.h.
#define PCI_STATUS_DEVSEL_FAST (0 << 9) |
Definition at line 194 of file pci_config.h.
#define PCI_STATUS_DEVSEL_GET | ( | x | ) | ((x >> 9) & 3) /* DEVSEL timing */ |
Definition at line 193 of file pci_config.h.
#define PCI_STATUS_DEVSEL_MEDIUM (1 << 9) |
Definition at line 195 of file pci_config.h.
#define PCI_STATUS_DEVSEL_SLOW (2 << 9) |
Definition at line 196 of file pci_config.h.
#define PCI_STATUS_INTX_PENDING (1 << 3) |
Definition at line 187 of file pci_config.h.
#define PCI_STATUS_PARITY_ERROR (1 << 8) /* Detected parity error */ |
Definition at line 192 of file pci_config.h.
#define PCI_STATUS_REC_MASTER_ABORT (1 << 13) /* Set on master abort */ |
Definition at line 199 of file pci_config.h.
#define PCI_STATUS_REC_TARGET_ABORT (1 << 12) /* Master ack of " */ |
Definition at line 198 of file pci_config.h.
#define PCI_STATUS_SIG_SYSTEM_ERROR (1 << 14) /* Set when we drive SERR */ |
Definition at line 200 of file pci_config.h.
#define PCI_STATUS_SIG_TARGET_ABORT (1 << 11) /* Set on target abort */ |
Definition at line 197 of file pci_config.h.
#define PCI_STATUS_UDF (1 << 6) /* Support User Definable Features (obsolete) */ |
Definition at line 190 of file pci_config.h.
#define PCI_VC_PORT_CTRL 12 |
Definition at line 705 of file pci_config.h.
#define PCI_VC_PORT_REG1 4 |
Definition at line 703 of file pci_config.h.
#define PCI_VC_PORT_REG2 8 |
Definition at line 704 of file pci_config.h.
#define PCI_VC_PORT_STATUS 14 |
Definition at line 706 of file pci_config.h.
#define PCI_VC_RES_CAP 16 |
Definition at line 707 of file pci_config.h.
#define PCI_VC_RES_CTRL 20 |
Definition at line 708 of file pci_config.h.
#define PCI_VC_RES_STATUS 26 |
Definition at line 709 of file pci_config.h.
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ |
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ |
#define PCIE_CAP_DEVICE_TYPE | ( | x | ) | (((x) >> 4) & 0xf) |
#define PCIE_CAP_MSI_IRQ | ( | x | ) | (((x) >> 9) & 0x1f) |
#define PCIE_CAP_SLOW_IMPLEMENTED (1 << 8) |
#define PCIE_CAP_VERSION | ( | x | ) | (((x) >> 0) & 0xf) |
#define PCIE_CTRL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ |
#define PCIE_CTRL_CERE 0x0001 /* Correctable Error Reporting En. */ |
#define PCIE_CTRL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ |
#define PCIE_CTRL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
#define PCIE_CTRL_MAX_PAYLOAD | ( | n | ) | (((n) & 7) << 5) |
#define PCIE_CTRL_MAX_READ_REQUEST | ( | n | ) | (((n) & 7) << 12) |
#define PCIE_CTRL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
#define PCIE_CTRL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ |
#define PCIE_CTRL_PHANTOM 0x0200 /* Phantom Functions Enable */ |
#define PCIE_CTRL_RELAX_EN 0x0010 /* Enable relaxed ordering */ |
#define PCIE_CTRL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
#define PCIE_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
#define PCIE_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
#define PCIE_DEVCAP_EXTENTED_TAG (1 << 5) |
#define PCIE_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
#define PCIE_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
#define PCIE_DEVCAP_MAX_PAYLOAD | ( | x | ) | (128 << (((x) >> 0) & 0x7)) |
#define PCIE_DEVCAP_PHANTOM_BITS | ( | x | ) | (((x) >> 3) & 0x3) |
#define PCIE_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
#define PCIE_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
#define PCIE_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
#define PCIE_DEVICE_TYPE_ENDPOINT 0 |
#define PCIE_DEVICE_TYPE_LEGACY_ENDPOINT 1 |
#define PCIE_DEVICE_TYPE_PCI_TO_PCIE_BRIDGE 8 |
#define PCIE_DEVICE_TYPE_PCIE_TO_PCI_BRIDGE 7 |
#define PCIE_DEVICE_TYPE_ROOT_COMPLEX_ENDPOINT 9 |
#define PCIE_DEVICE_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10 |
#define PCIE_DEVICE_TYPE_ROOT_PORT 4 |
#define PCIE_DEVICE_TYPE_SWITCH_DOWNSTREAM 6 |
#define PCIE_DEVICE_TYPE_SWITCH_UPSTREAM 5 |
#define PCIE_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
#define PCIE_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
#define PCIE_ERROR_COR_ADVISORY (1 << 13) |
#define PCIE_ERROR_COR_BAD_DLLP (1 << 7) |
#define PCIE_ERROR_COR_BAD_TLP (1 << 6) |
#define PCIE_ERROR_COR_REPLAY_ROLLOVER (1 << 8) |
#define PCIE_ERROR_COR_REPLAY_TIMER (1 << 12) |
#define PCIE_ERROR_COR_RX_ERROR (1 << 0) |
#define PCIE_ERROR_UNC_COMPLETER_ABORT (1 << 15) |
#define PCIE_ERROR_UNC_COMPLETION_TIMEOUT (1 << 14) |
#define PCIE_ERROR_UNC_CRC_ERROR (1 << 19) |
#define PCIE_ERROR_UNC_DATA_LINK_PROTOCOL (1 << 4) |
#define PCIE_ERROR_UNC_FLOW_CONTROL (1 << 13) |
#define PCIE_ERROR_UNC_LINK_TRAINING (1 << 0) |
#define PCIE_ERROR_UNC_MALFORMED_TLP (1 << 18) |
#define PCIE_ERROR_UNC_POISONED_TLP (1 << 12) |
#define PCIE_ERROR_UNC_RX_OVERFLOW (1 << 17) |
#define PCIE_ERROR_UNC_SURPRISE_DOWN (1 << 5) |
#define PCIE_ERROR_UNC_UNEXPECTED_COMPLETION (1 << 16) |
#define PCIE_ERROR_UNC_UNSUPPORTED_REQUEST (1 << 20) |
#define PCIE_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
#define PCIE_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
#define PCIE_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ |
#define PCIE_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
#define PCIE_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ |
#define PCIX_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
#define PCIX_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ |
#define PCIX_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ |
#define PCIX_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
#define PCIX_CMD_VERSION | ( | x | ) | (((x) >> 12) & 3) /* Version */ |
#define PCIX_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ |
#define PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
#define PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
#define PCIX_STATUS_64BIT 0x00010000 /* 64-bit device */ |
#define PCIX_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ |
#define PCIX_STATUS_COMPLEX 0x00100000 /* Device Complexity */ |
#define PCIX_STATUS_DEVFN 0x000000ff /* A copy of devfn */ |
#define PCIX_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ |
#define PCIX_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ |
#define PCIX_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ |
#define PCIX_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ |
#define PCIX_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
#define PCIX_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ |
typedef enum pci_capability_type pci_capability_type_t |
typedef enum pcie_capability_type pcie_capability_type_t |
enum pci_capability_type |
Enumerator | |
---|---|
PCI_CAP_ID_PM | |
PCI_CAP_ID_AGP | |
PCI_CAP_ID_VPD | |
PCI_CAP_ID_SLOTID | |
PCI_CAP_ID_MSI | |
PCI_CAP_ID_CHSWP | |
PCI_CAP_ID_PCIX | |
PCI_CAP_ID_HYPERTRANSPORT | |
PCI_CAP_ID_SHPC | |
PCI_CAP_ID_PCIE | |
PCI_CAP_ID_MSIX |
Definition at line 370 of file pci_config.h.
enum pci_device_class_t |
Definition at line 46 of file pci_config.h.
enum pcie_capability_type |
Enumerator | |
---|---|
PCIE_CAP_ADVANCED_ERROR | |
PCIE_CAP_VC | |
PCIE_CAP_DSN | |
PCIE_CAP_PWR |
Definition at line 654 of file pci_config.h.
typedef CLIB_PACKED | ( | struct{enum pci_capability_type type:8;u8 next_offset;} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u16 capabilities;#define PCI_PM_CAP_VER_MASK#define PCI_PM_CAP_PME_CLOCK#define PCI_PM_CAP_RESERVED#define PCI_PM_CAP_DSI#define PCI_PM_CAP_AUX_POWER#define PCI_PM_CAP_D1#define PCI_PM_CAP_D2#define PCI_PM_CAP_PME#define PCI_PM_CAP_PME_MASK#define PCI_PM_CAP_PME_D0#define PCI_PM_CAP_PME_D1#define PCI_PM_CAP_PME_D2#define PCI_PM_CAP_PME_D3#define PCI_PM_CAP_PME_D3cold u16 control;#define PCI_PM_CTRL_STATE_MASK#define PCI_PM_CTRL_PME_ENABLE#define PCI_PM_CTRL_DATA_SEL_MASK#define PCI_PM_CTRL_DATA_SCALE_MASK#define PCI_PM_CTRL_PME_STATUS u8 extensions;#define PCI_PM_PPB_B2_B3#define PCI_PM_BPCC_ENABLE u8 data;} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u8 version;u8 rest_of_capability_flags;u32 status;u32 command;#define PCI_AGP_RQ_MASK#define PCI_AGP_SBA#define PCI_AGP_64BIT#define PCI_AGP_ALLOW_TRANSACTIONS#define PCI_AGP_FW#define PCI_AGP_RATE4#define PCI_AGP_RATE2#define PCI_AGP_RATE1} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u16 address;#define PCI_VPD_ADDR_MASK#define PCI_VPD_ADDR_F u32 data;} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u8 esr;#define PCI_SID_ESR_NSLOTS#define PCI_SID_ESR_FIC u8 chassis;} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u16 flags;#define PCI_MSI_FLAGS_ENABLE#define PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE(x)#define PCI_MSI_FLAGS_MAX_QUEUE_SIZE(x)#define PCI_MSI_FLAGS_GET_QUEUE_SIZE(x)#define PCI_MSI_FLAGS_QUEUE_SIZE(x)#define PCI_MSI_FLAGS_64BIT#define PCI_MSI_FLAGS_MASKBIT u32 address;u32 data;u32 mask_bits;} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u16 flags;u32 address[2];u32 data;u32 mask_bits;} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u16 control_status;#define PCI_CHSWP_DHA#define PCI_CHSWP_EIM#define PCI_CHSWP_PIE#define PCI_CHSWP_LOO#define PCI_CHSWP_PI#define PCI_CHSWP_EXT#define PCI_CHSWP_INS} | ) |
typedef CLIB_PACKED | ( | struct{pci_capability_regs_t header;u16 command;#define PCIX_CMD_DPERR_E#define PCIX_CMD_ERO#define PCIX_CMD_MAX_READ#define PCIX_CMD_MAX_SPLIT#define PCIX_CMD_VERSION(x) u32 status;#define PCIX_STATUS_DEVFN#define PCIX_STATUS_BUS#define PCIX_STATUS_64BIT#define PCIX_STATUS_133MHZ#define PCIX_STATUS_SPL_DISC#define PCIX_STATUS_UNX_SPL#define PCIX_STATUS_COMPLEX#define PCIX_STATUS_MAX_READ#define PCIX_STATUS_MAX_SPLIT#define PCIX_STATUS_MAX_CUM#define PCIX_STATUS_SPL_ERR#define PCIX_STATUS_266MHZ#define PCIX_STATUS_533MHZ} | ) |
typedef CLIB_PACKED | ( | struct{enum pcie_capability_type type:16;u16 version:4;u16 next_capability:12;} | ) |
typedef CLIB_PACKED | ( | struct{pcie_capability_regs_t header;u32 uncorrectable_status;#define PCIE_ERROR_UNC_LINK_TRAINING#define PCIE_ERROR_UNC_DATA_LINK_PROTOCOL#define PCIE_ERROR_UNC_SURPRISE_DOWN#define PCIE_ERROR_UNC_POISONED_TLP#define PCIE_ERROR_UNC_FLOW_CONTROL#define PCIE_ERROR_UNC_COMPLETION_TIMEOUT#define PCIE_ERROR_UNC_COMPLETER_ABORT#define PCIE_ERROR_UNC_UNEXPECTED_COMPLETION#define PCIE_ERROR_UNC_RX_OVERFLOW#define PCIE_ERROR_UNC_MALFORMED_TLP#define PCIE_ERROR_UNC_CRC_ERROR#define PCIE_ERROR_UNC_UNSUPPORTED_REQUEST u32 uncorrectable_mask;u32 uncorrectable_severity;u32 correctable_status;#define PCIE_ERROR_COR_RX_ERROR#define PCIE_ERROR_COR_BAD_TLP#define PCIE_ERROR_COR_BAD_DLLP#define PCIE_ERROR_COR_REPLAY_ROLLOVER#define PCIE_ERROR_COR_REPLAY_TIMER#define PCIE_ERROR_COR_ADVISORY u32 correctable_mask;u32 control;u32 log[4];u32 root_command;u32 root_status;u16 correctable_error_source;u16 error_source;} | ) |
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Definition at line 415 of file pci_config.h.
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Definition at line 272 of file pci_config.h.
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Definition at line 346 of file pci_config.h.
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Definition at line 159 of file pci_config.h.
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