40 #ifndef included_vlib_pci_config_h 41 #define included_vlib_pci_config_h 174 #define PCI_COMMAND_IO (1 << 0) 175 #define PCI_COMMAND_MEMORY (1 << 1) 176 #define PCI_COMMAND_BUS_MASTER (1 << 2) 177 #define PCI_COMMAND_SPECIAL (1 << 3) 178 #define PCI_COMMAND_WRITE_INVALIDATE (1 << 4) 179 #define PCI_COMMAND_VGA_PALETTE_SNOOP (1 << 5) 180 #define PCI_COMMAND_PARITY (1 << 6) 181 #define PCI_COMMAND_WAIT (1 << 7) 182 #define PCI_COMMAND_SERR (1 << 8) 183 #define PCI_COMMAND_BACK_TO_BACK_WRITE (1 << 9) 184 #define PCI_COMMAND_INTX_DISABLE (1 << 10) 187 #define PCI_STATUS_INTX_PENDING (1 << 3) 188 #define PCI_STATUS_CAPABILITY_LIST (1 << 4) 189 #define PCI_STATUS_66MHZ (1 << 5) 190 #define PCI_STATUS_UDF (1 << 6) 191 #define PCI_STATUS_BACK_TO_BACK_WRITE (1 << 7) 192 #define PCI_STATUS_PARITY_ERROR (1 << 8) 193 #define PCI_STATUS_DEVSEL_GET(x) ((x >> 9) & 3) 194 #define PCI_STATUS_DEVSEL_FAST (0 << 9) 195 #define PCI_STATUS_DEVSEL_MEDIUM (1 << 9) 196 #define PCI_STATUS_DEVSEL_SLOW (2 << 9) 197 #define PCI_STATUS_SIG_TARGET_ABORT (1 << 11) 198 #define PCI_STATUS_REC_TARGET_ABORT (1 << 12) 199 #define PCI_STATUS_REC_MASTER_ABORT (1 << 13) 200 #define PCI_STATUS_SIG_SYSTEM_ERROR (1 << 14) 201 #define PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15) 212 #define PCI_HEADER_TYPE_NORMAL 0 213 #define PCI_HEADER_TYPE_BRIDGE 1 214 #define PCI_HEADER_TYPE_CARDBUS 2 217 #define PCI_BIST_CODE_MASK 0x0f 218 #define PCI_BIST_START 0x40 219 #define PCI_BIST_CAPABLE 0x80 228 #define _(f,t) r->f = clib_byte_swap_##t (r->f) 233 _(device_class,
u16);
256 #define PCI_ROM_ADDRESS 0x30 257 #define PCI_ROM_ADDRESS_ENABLE 0x01 258 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 261 CLIB_PAD_FROM_TO (0x35, 0x3c);
268 u8 capability_data[0];
278 #define _(f,t) r->f = clib_byte_swap_##t (r->f) 280 _(base_address[i],
u32);
282 _(subsystem_vendor_id,
u16);
283 _(subsystem_id,
u16);
312 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 313 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 316 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 317 #define PCI_PREF_RANGE_TYPE_32 0x00 318 #define PCI_PREF_RANGE_TYPE_64 0x01 319 #define PCI_PREF_RANGE_MASK (~0x0fUL) 328 CLIB_PAD_FROM_TO (0x35, 0x37);
331 CLIB_PAD_FROM_TO (0x3c, 0x3e);
334 #define PCI_BRIDGE_CTL_PARITY 0x01 335 #define PCI_BRIDGE_CTL_SERR 0x02 336 #define PCI_BRIDGE_CTL_NO_ISA 0x04 337 #define PCI_BRIDGE_CTL_VGA 0x08 338 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 339 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 340 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 342 u8 capability_data[0];
352 #define _(f,t) r->f = clib_byte_swap_##t (r->f) 354 _(base_address[i],
u32);
355 _(secondary_status,
u16);
357 _(memory_limit,
u16);
358 _(prefetchable_memory_base,
u16);
359 _(prefetchable_memory_limit,
u16);
360 _(prefetchable_memory_base_upper_32bits,
u32);
361 _(prefetchable_memory_limit_upper_32bits,
u32);
362 _(io_base_upper_16bits,
u16);
363 _(io_limit_upper_16bits,
u16);
365 _(bridge_control,
u16);
411 u8 next_offset;}) pci_capability_regs_t;
417 pci_capability_regs_t *
c;
425 while (ttl-- && next_offset >= 0x40)
427 c = (
void *) t + (next_offset & ~3);
428 if ((
u8) c->type == 0xff)
430 if (c->type == cap_type)
432 next_offset = c->next_offset;
441 pci_capability_regs_t header;
u16 capabilities;
442 #define PCI_PM_CAP_VER_MASK 0x0007 443 #define PCI_PM_CAP_PME_CLOCK 0x0008 444 #define PCI_PM_CAP_RESERVED 0x0010 445 #define PCI_PM_CAP_DSI 0x0020 446 #define PCI_PM_CAP_AUX_POWER 0x01C0 447 #define PCI_PM_CAP_D1 0x0200 448 #define PCI_PM_CAP_D2 0x0400 449 #define PCI_PM_CAP_PME 0x0800 450 #define PCI_PM_CAP_PME_MASK 0xF800 451 #define PCI_PM_CAP_PME_D0 0x0800 452 #define PCI_PM_CAP_PME_D1 0x1000 453 #define PCI_PM_CAP_PME_D2 0x2000 454 #define PCI_PM_CAP_PME_D3 0x4000 455 #define PCI_PM_CAP_PME_D3cold 0x8000 457 #define PCI_PM_CTRL_STATE_MASK 0x0003 458 #define PCI_PM_CTRL_PME_ENABLE 0x0100 459 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 460 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 461 #define PCI_PM_CTRL_PME_STATUS 0x8000 463 #define PCI_PM_PPB_B2_B3 0x40 464 #define PCI_PM_BPCC_ENABLE 0x80 465 u8 data;}) pci_power_management_regs_t;
472 pci_capability_regs_t header;
u8 version;
473 u8 rest_of_capability_flags;
u32 status;
u32 command;
475 #define PCI_AGP_RQ_MASK 0xff000000 476 #define PCI_AGP_SBA 0x0200 477 #define PCI_AGP_64BIT 0x0020 478 #define PCI_AGP_ALLOW_TRANSACTIONS 0x0100 479 #define PCI_AGP_FW 0x0010 480 #define PCI_AGP_RATE4 0x0004 481 #define PCI_AGP_RATE2 0x0002 482 #define PCI_AGP_RATE1 0x0001 490 pci_capability_regs_t header;
u16 address;
491 #define PCI_VPD_ADDR_MASK 0x7fff 492 #define PCI_VPD_ADDR_F 0x8000 493 u32 data;}) pci_vpd_regs_t;
500 pci_capability_regs_t header;
u8 esr;
501 #define PCI_SID_ESR_NSLOTS 0x1f 502 #define PCI_SID_ESR_FIC 0x20 503 u8 chassis;}) pci_sid_regs_t;
510 pci_capability_regs_t header;
u16 flags;
511 #define PCI_MSI_FLAGS_ENABLE (1 << 0) 512 #define PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE(x) ((x >> 1) & 0x7) 513 #define PCI_MSI_FLAGS_MAX_QUEUE_SIZE(x) (((x) & 0x7) << 1) 514 #define PCI_MSI_FLAGS_GET_QUEUE_SIZE(x) ((x >> 4) & 0x7) 515 #define PCI_MSI_FLAGS_QUEUE_SIZE(x) (((x) & 0x7) << 4) 516 #define PCI_MSI_FLAGS_64BIT (1 << 7) 517 #define PCI_MSI_FLAGS_MASKBIT (1 << 8) 518 u32 address;
u32 data;
u32 mask_bits;}) pci_msi32_regs_t;
524 pci_capability_regs_t header;
u16 flags;
526 u32 data;
u32 mask_bits;}) pci_msi64_regs_t;
533 pci_capability_regs_t header;
u16 control_status;
534 #define PCI_CHSWP_DHA 0x01 535 #define PCI_CHSWP_EIM 0x02 536 #define PCI_CHSWP_PIE 0x04 537 #define PCI_CHSWP_LOO 0x08 538 #define PCI_CHSWP_PI 0x30 539 #define PCI_CHSWP_EXT 0x40 540 #define PCI_CHSWP_INS 0x80 548 pci_capability_regs_t header;
u16 command;
549 #define PCIX_CMD_DPERR_E 0x0001 550 #define PCIX_CMD_ERO 0x0002 551 #define PCIX_CMD_MAX_READ 0x000c 552 #define PCIX_CMD_MAX_SPLIT 0x0070 553 #define PCIX_CMD_VERSION(x) (((x) >> 12) & 3) 555 #define PCIX_STATUS_DEVFN 0x000000ff 556 #define PCIX_STATUS_BUS 0x0000ff00 557 #define PCIX_STATUS_64BIT 0x00010000 558 #define PCIX_STATUS_133MHZ 0x00020000 559 #define PCIX_STATUS_SPL_DISC 0x00040000 560 #define PCIX_STATUS_UNX_SPL 0x00080000 561 #define PCIX_STATUS_COMPLEX 0x00100000 562 #define PCIX_STATUS_MAX_READ 0x00600000 563 #define PCIX_STATUS_MAX_SPLIT 0x03800000 564 #define PCIX_STATUS_MAX_CUM 0x1c000000 565 #define PCIX_STATUS_SPL_ERR 0x20000000 566 #define PCIX_STATUS_266MHZ 0x40000000 567 #define PCIX_STATUS_533MHZ 0x80000000 568 }) pcix_config_regs_t;
582 int size = 1 << (code + 7);
591 pci_capability_regs_t header;
u16 pcie_capabilities;
592 #define PCIE_CAP_VERSION(x) (((x) >> 0) & 0xf) 593 #define PCIE_CAP_DEVICE_TYPE(x) (((x) >> 4) & 0xf) 594 #define PCIE_DEVICE_TYPE_ENDPOINT 0 595 #define PCIE_DEVICE_TYPE_LEGACY_ENDPOINT 1 596 #define PCIE_DEVICE_TYPE_ROOT_PORT 4 598 #define PCIE_DEVICE_TYPE_SWITCH_UPSTREAM 5 599 #define PCIE_DEVICE_TYPE_SWITCH_DOWNSTREAM 6 600 #define PCIE_DEVICE_TYPE_PCIE_TO_PCI_BRIDGE 7 601 #define PCIE_DEVICE_TYPE_PCI_TO_PCIE_BRIDGE 8 603 #define PCIE_DEVICE_TYPE_ROOT_COMPLEX_ENDPOINT 9 604 #define PCIE_DEVICE_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10 605 #define PCIE_CAP_SLOW_IMPLEMENTED (1 << 8) 606 #define PCIE_CAP_MSI_IRQ(x) (((x) >> 9) & 0x1f) 607 u32 dev_capabilities;
608 #define PCIE_DEVCAP_MAX_PAYLOAD(x) (128 << (((x) >> 0) & 0x7)) 609 #define PCIE_DEVCAP_PHANTOM_BITS(x) (((x) >> 3) & 0x3) 610 #define PCIE_DEVCAP_EXTENTED_TAG (1 << 5) 611 #define PCIE_DEVCAP_L0S 0x1c0 612 #define PCIE_DEVCAP_L1 0xe00 613 #define PCIE_DEVCAP_ATN_BUT 0x1000 614 #define PCIE_DEVCAP_ATN_IND 0x2000 615 #define PCIE_DEVCAP_PWR_IND 0x4000 616 #define PCIE_DEVCAP_PWR_VAL 0x3fc0000 617 #define PCIE_DEVCAP_PWR_SCL 0xc000000 619 #define PCIE_CTRL_CERE 0x0001 620 #define PCIE_CTRL_NFERE 0x0002 621 #define PCIE_CTRL_FERE 0x0004 622 #define PCIE_CTRL_URRE 0x0008 623 #define PCIE_CTRL_RELAX_EN 0x0010 624 #define PCIE_CTRL_MAX_PAYLOAD(n) (((n) & 7) << 5) 625 #define PCIE_CTRL_EXT_TAG 0x0100 626 #define PCIE_CTRL_PHANTOM 0x0200 627 #define PCIE_CTRL_AUX_PME 0x0400 628 #define PCIE_CTRL_NOSNOOP_EN 0x0800 629 #define PCIE_CTRL_MAX_READ_REQUEST(n) (((n) & 7) << 12) 631 #define PCIE_DEVSTA_AUXPD 0x10 632 #define PCIE_DEVSTA_TRPND 0x20 633 u32 link_capabilities;
u16 link_control;
u16 link_status;
634 u32 slot_capabilities;
635 u16 slot_control;
u16 slot_status;
u16 root_control;
636 #define PCIE_RTCTL_SECEE 0x01 637 #define PCIE_RTCTL_SENFEE 0x02 638 #define PCIE_RTCTL_SEFEE 0x04 639 #define PCIE_RTCTL_PMEIE 0x08 640 #define PCIE_RTCTL_CRSSVE 0x10 641 u16 root_capabilities;
643 u32 dev_capabilities2;
646 u32 link_capabilities2;
649 u32 slot_capabilities2;
u16 slot_control2;
650 u16 slot_status2;}) pcie_config_regs_t;
668 pcie_capability_regs_t;
673 pcie_capability_regs_t header;
u32 uncorrectable_status;
674 #define PCIE_ERROR_UNC_LINK_TRAINING (1 << 0) 675 #define PCIE_ERROR_UNC_DATA_LINK_PROTOCOL (1 << 4) 676 #define PCIE_ERROR_UNC_SURPRISE_DOWN (1 << 5) 677 #define PCIE_ERROR_UNC_POISONED_TLP (1 << 12) 678 #define PCIE_ERROR_UNC_FLOW_CONTROL (1 << 13) 679 #define PCIE_ERROR_UNC_COMPLETION_TIMEOUT (1 << 14) 680 #define PCIE_ERROR_UNC_COMPLETER_ABORT (1 << 15) 681 #define PCIE_ERROR_UNC_UNEXPECTED_COMPLETION (1 << 16) 682 #define PCIE_ERROR_UNC_RX_OVERFLOW (1 << 17) 683 #define PCIE_ERROR_UNC_MALFORMED_TLP (1 << 18) 684 #define PCIE_ERROR_UNC_CRC_ERROR (1 << 19) 685 #define PCIE_ERROR_UNC_UNSUPPORTED_REQUEST (1 << 20) 686 u32 uncorrectable_mask;
687 u32 uncorrectable_severity;
u32 correctable_status;
688 #define PCIE_ERROR_COR_RX_ERROR (1 << 0) 689 #define PCIE_ERROR_COR_BAD_TLP (1 << 6) 690 #define PCIE_ERROR_COR_BAD_DLLP (1 << 7) 691 #define PCIE_ERROR_COR_REPLAY_ROLLOVER (1 << 8) 692 #define PCIE_ERROR_COR_REPLAY_TIMER (1 << 12) 693 #define PCIE_ERROR_COR_ADVISORY (1 << 13) 694 u32 correctable_mask;
698 u32 root_status;
u16 correctable_error_source;
699 u16 error_source;}) pcie_advanced_error_regs_t;
703 #define PCI_VC_PORT_REG1 4 704 #define PCI_VC_PORT_REG2 8 705 #define PCI_VC_PORT_CTRL 12 706 #define PCI_VC_PORT_STATUS 14 707 #define PCI_VC_RES_CAP 16 708 #define PCI_VC_RES_CTRL 20 709 #define PCI_VC_RES_STATUS 26 712 #define PCI_PWR_DSR 4 713 #define PCI_PWR_DATA 8 714 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 715 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 716 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 717 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 718 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 719 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 720 #define PCI_PWR_CAP 12 721 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) static pci_device_class_t pci_device_class_base(pci_device_class_t c)
pci_config_header_t header
sll srl srl sll sra u16x4 i
u8 capability_list_offset
static void * pci_config_find_capability(pci_config_type0_regs_t *t, int cap_type)
enum pcie_capability_type pcie_capability_type_t
enum pci_capability_type pci_capability_type_t
static void pci_config_header_little_to_host(pci_config_header_t *r)
static uword min_log2(uword x)
u16 prefetchable_memory_limit
static void pci_config_type1_little_to_host(pci_config_type1_regs_t *r)
u16 io_limit_upper_16bits
u8 first_capability_offset
static int pcie_size_to_code(int bytes)
u8 secondary_bus_latency_timer
static void pci_config_type0_little_to_host(pci_config_type0_regs_t *r)
#define PCI_STATUS_CAPABILITY_LIST
typedef CLIB_PACKED(struct{enum pci_capability_type type:8;u8 next_offset;}) pci_capability_regs_t
static uword is_pow2(uword x)
#define CLIB_ARCH_IS_BIG_ENDIAN
u32 prefetchable_memory_limit_upper_32bits
static int pcie_code_to_size(int code)
u32 prefetchable_memory_base_upper_32bits
pci_config_header_t header