20 #define foreach_x86_cpu_uarch \
21 _(0x06, 0x9e, "Kaby Lake", "Kaby Lake DT/H/S/X") \
22 _(0x06, 0x8e, "Kaby Lake", "Kaby Lake Y/U") \
23 _(0x06, 0x8c, "Tiger Lake", "Tiger Lake U") \
24 _(0x06, 0x86, "Tremont", "Elkhart Lake") \
25 _(0x06, 0x85, "Knights Mill", "Knights Mill") \
26 _(0x06, 0x7e, "Ice Lake", "Ice Lake U") \
27 _(0x06, 0x7d, "Ice Lake", "Ice Lake Y") \
28 _(0x06, 0x7a, "Goldmont Plus", "Gemini Lake") \
29 _(0x06, 0x6c, "Ice Lake", "Ice Lake SP") \
30 _(0x06, 0x6a, "Ice Lake", "Ice Lake DE") \
31 _(0x06, 0x66, "Cannon Lake", "Cannon Lake U") \
32 _(0x06, 0x5f, "Goldmont", "Denverton") \
33 _(0x06, 0x5e, "Skylake", "Skylake DT/H/S") \
34 _(0x06, 0x5c, "Goldmont", "Apollo Lake") \
35 _(0x06, 0x5a, "Silvermont", "Moorefield") \
36 _(0x06, 0x57, "Knights Landing", "Knights Landing") \
37 _(0x06, 0x56, "Broadwell", "Broadwell DE") \
38 _(0x06, 0x55, "Skylake", "Skylake X/SP") \
39 _(0x06, 0x4f, "Broadwell", "Broadwell EP/EX") \
40 _(0x06, 0x4e, "Skylake", "Skylake Y/U") \
41 _(0x06, 0x4d, "Silvermont", "Rangeley") \
42 _(0x06, 0x4c, "Airmont", "Braswell") \
43 _(0x06, 0x47, "Broadwell", "Broadwell H") \
44 _(0x06, 0x46, "Haswell", "Crystalwell") \
45 _(0x06, 0x45, "Haswell", "Haswell ULT") \
46 _(0x06, 0x3f, "Haswell", "Haswell E") \
47 _(0x06, 0x3e, "Ivy Bridge", "Ivy Bridge E/EN/EP") \
48 _(0x06, 0x3d, "Broadwell", "Broadwell U") \
49 _(0x06, 0x3c, "Haswell", "Haswell") \
50 _(0x06, 0x3a, "Ivy Bridge", "IvyBridge") \
51 _(0x06, 0x37, "Silvermont", "BayTrail") \
52 _(0x06, 0x36, "Saltwell", "Cedarview,Centerton") \
53 _(0x06, 0x35, "Saltwell", "Cloverview") \
54 _(0x06, 0x2f, "Westmere", "Westmere EX") \
55 _(0x06, 0x2e, "Nehalem", "Nehalem EX") \
56 _(0x06, 0x2d, "Sandy Bridge", "SandyBridge E/EN/EP") \
57 _(0x06, 0x2c, "Westmere", "Westmere EP/EX,Gulftown") \
58 _(0x06, 0x2a, "Sandy Bridge", "Sandy Bridge") \
59 _(0x06, 0x27, "Saltwell", "Medfield") \
60 _(0x06, 0x26, "Bonnell", "Tunnel Creek") \
61 _(0x06, 0x25, "Westmere", "Arrandale,Clarksdale") \
62 _(0x06, 0x1e, "Nehalem", "Clarksfield,Lynnfield,Jasper Forest") \
63 _(0x06, 0x1d, "Penryn", "Dunnington") \
64 _(0x06, 0x1c, "Bonnell", "Pineview,Silverthorne") \
65 _(0x06, 0x1a, "Nehalem", "Nehalem EP,Bloomfield)") \
66 _(0x06, 0x17, "Penryn", "Yorkfield,Wolfdale,Penryn,Harpertown")
69 #define foreach_aarch64_cpu_uarch \
70 _(0x41, 0xd03, "ARM", "Cortex-A53", 0) \
71 _(0x41, 0xd07, "ARM", "Cortex-A57", 0) \
72 _(0x41, 0xd08, "ARM", "Cortex-A72", 0) \
73 _(0x41, 0xd09, "ARM", "Cortex-A73", 0) \
74 _(0x41, 0xd0a, "ARM", "Cortex-A75", 0) \
75 _(0x41, 0xd0b, "ARM", "Cortex-A76", 0) \
76 _(0x41, 0xd0c, "ARM", "Neoverse-N1", 0) \
77 _(0x41, 0xd4a, "ARM", "Neoverse-E1", 0) \
78 _(0x43, 0x0a1, "Marvell", "THUNDERX CN88XX", 0) \
79 _(0x43, 0x0a2, "Marvell", "OCTEON TX CN81XX", 0) \
80 _(0x43, 0x0a3, "Marvell", "OCTEON TX CN83XX", 0) \
81 _(0x43, 0x0af, "Marvell", "THUNDERX2 CN99XX", 1) \
82 _(0x43, 0x0b1, "Marvell", "OCTEON TX2 CN98XX", 1) \
83 _(0x43, 0x0b2, "Marvell", "OCTEON TX2 CN96XX", 1)
89 u32 __attribute__ ((unused)) eax, ebx, ecx, edx;
90 u8 model, family, stepping;
92 if (__get_cpuid (1, &eax, &ebx, &ecx, &edx) == 0)
93 return format (s,
"unknown (missing cpuid)");
95 model = ((eax >> 4) & 0x0f) | ((eax >> 12) & 0xf0);
96 family = (eax >> 8) & 0x0f;
97 stepping = eax & 0x0f;
99 #define _(f,m,a,c) if ((model == m) && (family == f)) return \
100 format(s, "[0x%x] %s ([0x%02x] %s) stepping 0x%x", f, a, m, c, stepping);
103 return format (s,
"unknown (family 0x%02x model 0x%02x)", family, model);
108 u32 implementer, primary_part_number, variant, revision;
110 fd = open (
"/proc/cpuinfo", 0);
112 return format (s,
"unknown");
117 if (
unformat (&input,
"CPU implementer%_: 0x%x", &implementer))
119 else if (
unformat (&input,
"CPU part%_: 0x%x", &primary_part_number))
121 else if (
unformat (&input,
"CPU variant%_: 0x%x", &variant))
123 else if (
unformat (&input,
"CPU revision%_: %u", &revision))
131 #define _(i,p,a,c,_format) if ((implementer == i) && (primary_part_number == p)){ \
133 return format(s, "%s (%s PASS %c%u)", a, c, 'A'+variant, revision);\
135 if (implementer == 0x43)\
137 return format (s, "%s (%s PASS %u.%u)", a, c, variant, revision);}}
141 return format (s,
"unknown (implementer 0x%02x part 0x%03x PASS %u.%u)",
142 implementer, primary_part_number, variant, revision);
145 return format (s,
"unknown");
153 u32 __attribute__ ((unused)) eax, ebx, ecx, edx;
157 if (__get_cpuid (1, &eax, &ebx, &ecx, &edx) == 0)
158 return format (s,
"unknown (missing cpuid)");
160 __get_cpuid (0x80000000, &eax, &ebx, &ecx, &edx);
161 if (eax < 0x80000004)
162 return format (s,
"unknown (missing ext feature)");
167 __get_cpuid (0x80000002, &eax, &ebx, &ecx, &edx);
173 __get_cpuid (0x80000003, &eax, &ebx, &ecx, &edx);
179 __get_cpuid (0x80000004, &eax, &ebx, &ecx, &edx);
189 #elif defined(__aarch64__)
190 return format (s,
"armv8");
192 return format (s,
"unknown");
197 static inline char const *
200 if (0 == strncmp (flag, pfx,
len - 1))
201 return flag +
len - 1;
208 #if defined(__x86_64__)
209 #define _(flag, func, reg, bit) \
210 if (clib_cpu_supports_ ## flag()) \
211 s = format (s, "%s ", flag_skip_prefix(#flag, "x86_", sizeof("x86_")));
214 #elif defined(__aarch64__)
215 #define _(flag, bit) \
216 if (clib_cpu_supports_ ## flag()) \
217 s = format (s, "%s ", flag_skip_prefix(#flag, "aarch64_", sizeof("aarch64_")));
221 return format (s,
"unknown");
229 syscall (__NR_getcpu, &cpu, &
node, 0);
237 syscall (__NR_getcpu, &cpu, &
node, 0);
245 char *variants[] = { [0] =
"default",
246 #define _(s, n) [CLIB_MARCH_VARIANT_TYPE_##s] = n,
250 return format (s,
"%s", variants[t]);